MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 119

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 0008 (Hex)
Label: IDR
Reset Value: 0000 (Hex)
Address: 0006 (Hex)
Label: HAIC
Reset Value: 0000 (Hex)
ACC_DONE_SE
RD_N_WR
Reserved
Label
Label
AEM
HAB
ACC
IDV
Position
Position
15:0
15:9
Bit
4:0
Bit
5
6
7
8
Table 29 - High Address Indirection Command Register
Type
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/O
Table 30 - Indirection Data Register
Indirection Data Value.
During an indirection write cycle, the value written to this register is placed in the memory
location selected in the LAWI and HAIC registers. During an indirection read cycle, the
contents of the memory location selected in LAWI and HAIC are transferred to this register.
In the case of a write cycle, this register must be written before the LAWI and HAIC
registers. The CPU must wait for the ACC bit in the HAIC Register to be cleared before
initiating the next write cycle.
In the case of a read access to memory, the CPU must write the target address to the LAWI
and HAIC registers and wait for ACC = 0 before reading this register.
High Address Bits.
These bits represent bits<20:16> of the indirection address (in bytes).
Access External Memory.
When this bit is set, the indirection access will be to/from external memory. When this bit is
cleared, the indirection access will be to/from internal memory.
Read/Write.
‘0’ = CPU write.
‘1’ = CPU read.
Access Cycle Complete.
When this bit is set by the CPU, the indirection cycle is initiated. When low, indicates that
the last indirection cycle has been completed.
While an indirection access is in progress, the Microprocessor Interface Module registers
can be accessed.
However, the CPU must wait for the ACC bit to be cleared before initiating the next access
to another register block, internal memory, or external memory of the MT90520.
Software cannot clear this bit (it can only be cleared by hardware).
Access Cycle Complete Service Enable.
When this bit is set and the ACC bit is low, the CPU_SRV status bit is set in the Main
Status Register at 0002h.
Always read “0000_000”.
Zarlink Semiconductor Inc.
MT90520
119
Description
Description
Data Sheet