MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 67

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT90520
Data Sheet
The UDT RX_SAR and SDT RX_SAR modules are explained in the following sections.
In Section 4.6.1.2, the use of Reassembly Control Structures is detailed. These control structures, which are stored
in internal memory, control the operation of the UDT RX_SAR and the SDT RX_SAR on a per-VC basis.
The flow of the documentation starting in Section 4.6.1.3 on page 71 generally follows the flow of received cells
through the data path shown in Figure 26.
4.6.1.2
Reassembly Control Structures
The UDT RX_SAR and the SDT RX_SAR are both instantiated only once per MT90520 device. As a result, each
module must handle all of the cells being received at the device in a particular mode of operation. However, due to
the nature of the device, it is possible for multiple cell streams (i.e., cells being carried on different VCs) to be
received at the MT90520’s UTOPIA receive interface and then sent for processing by one of the RX_SARs. In order
to keep statistics and other information (e.g., current state of the Correction/Detection state machine, last received
sequence number) updated on a per-VC basis, the MT90520 employs two internal memories (one each for the
UDT RX_SAR and the SDT RX_SAR) to hold Reassembly Control Structures. The user must configure a control
structure for each VC which is receiving cells via the MT90520.
UDT Reassembly Control Structures
Within the UDT RX_SAR, there is an internal memory which can be configured to hold up to 8 UDT Reassembly
Control Structures (one per port). Each UDT Reassembly Control Structure is allocated a 32-byte block. The control
structures for the various ports must be located at pre-defined locations within the internal memory. If the data on a
VC is destined for port 0, the UDT Reassembly Control Structure for the VC must be programmed to begin at CPU
byte-address BE000h (the base address for the UDT Reassembly Control Structure memory in the MT90520
memory map). The control structure for a VC destined for port 1 must be configured to start at CPU byte-address
BE020h, and so on.
All of the fields within the control structure are explained in the text accompanying Figure 27. Upon initialization,
only a few of the fields within the UDT Reassembly Control Structure need to be explicitly configured by the user.
VC TDM Port must be configured to match the desired destination port for the VC’s data. As such, the only
permissible values for this field are “000” (representing port 0) to “111” (representing port 7). If SRTS or Adaptive
clock recovery methods are to be employed on the VC, the appropriate configuration bit (either S or A) must be set.
As well, the Maximum Lead field must be configured to a value which accounts for the expected cell delay
variation (CDV) of the network, and the desired distance to be maintained between the UDT RX_SAR’s write
pointer and the TDM module’s read pointer. More details regarding the programming of Maximum Lead are given
within the section “UDT Reassembly Circular Buffers” on page 78. All of the remaining fields within the UDT
Reassembly Control Structure must be cleared to ‘0’ upon initialization. This ensures that the statistics and status
fields for the VC are configured to start with cleared values.
For debug and statistics-gathering purposes, the CPU can read the UDT Reassembly Control Structure contents.
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