MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 137

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 5000 (Hex)
Label: CMCR
Reset Value: 0001 (Hex)
Note 1: Two rates for the FNXI clocks are provided in case different ports of the device are programmed to have SDT timing VCs carrying
different numbers of channels.
Note 2: Since RTS support is only provided in SDT mode for VCs carrying up to 32 channels, FNXI rates of 4.86 MHz and 9.72 MHz should
not be used.
BACKPLANE_CLK
_CONFIGURED
FNXI1_RATE
FNXI2_RATE
Reserved
Label
Position
15:13
11:9
Bit
8:6
12
Table 73 - Clock Management Configuration Register
Type
R/W
R/W
R/W
R/O
FNXI Rate Selector 1. (See Notes 1 and 2)
These bits are used to select the rate of the FNXI clock (#1) from which outgoing RTS
values will be generated, and to which incoming RTS values will be compared:
“000” = 75,937.5 Hz
“001” = 151,875 Hz
“010” = 303,750 Hz
“011” = 607,500 Hz
“100” = 1.215 MHz
“101” = 2.43 MHz (UDT rate)
“110” = 4.86 MHz
“111” = 9.72 MHz.
FNXI Rate Selector 2. (See Notes 1 and 2)
These bits are used to select the rate of the FNXI clock (#2) from which outgoing RTS
values will be generated, and to which incoming RTS values will be compared:
“000” = 75,937.5 Hz
“001” = 151,875 Hz
“010” = 303,750 Hz
“011” = 607,500 Hz
“100” = 1.215 MHz
“101” = 2.43 MHz (UDT rate)
“110” = 4.86 MHz
“111” = 9.72 MHz.
TDM Backplane Clock Configured
Must be set once the C4M_C2M and F0 signals are stable.
This bit needs to be high in order to ensure the synchronization of the TDM ports
programmed in backplane mode. A toggle of this bit resets the synchronization of all the
TDM ports programmed in backplane mode.
Always reads “000”.
Zarlink Semiconductor Inc.
MT90520
137
Description
Data Sheet