MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 59

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.5.2.2
Generally speaking, the generation of CBR cells in UDT mode is performed automatically by the TX_SAR, without
any CPU intervention being required. The TDM module reads data from the TDM bus and stores it in 47-byte
blocks in internal memory. When a block of memory is full, the TDM module sends an internal flag to the TX_SAR
module, indicating that it is time to generate a cell. The TX_SAR prepends the 47-byte block of data with an AAL1
header byte consisting of an in-order sequence number and related protection fields. The resulting 48-byte block is
then prepended with the 6-byte ATM cell header as configured via the fields in the UDT Segmentation Control
Structure for the VC. The complete cells are then transferred to the UTOPIA module for transmission onto the ATM
network.
Figure 21 below shows the complete segmentation data path in UDT mode, from the incoming TDM data bus to the
outgoing UTOPIA data bus.
4.5.3
In the SDT mode of operation, the TX_SAR is capable of generating cells on multiple VCs, independent of the
originating port on which the TDM data to be transmitted was received. Specifically, the TX_SAR is capable of
generating cells for a maximum of 256 different VCs (the equivalent of 32 VCs originating from each of the TDM
ports) in SDT mode. Unlike UDT mode, a single SDT VC does not need to transmit all of the data from a particular
port. Instead, VCs can contain various combinations of channels, ranging from N=1 VCs to VCs carrying up to 128
channels, in accordance with the af-vtoa-0089.000 standard for AAL1 narrowband trunking.
4.5.3.1
SDT Segmentation Control Structures
There must be one control structure for each SDT VC that the TX_SAR is to transmit. The format for the SDT
Segmentation Control Structures is shown in Figure 22. SDT control structures may be located at any address
within the internal memory space (starting at byte address 80000h) which is reserved for Segmentation Control
Structures.
UTO_OUT_ENBATM_CLAVPHY
UTO_OUT_CLAVATM_ENBPHY
SDT Mode of Operation
UTO_OUT_DATA[15:0]
Operation
Control Structure Configuration
UTO_OUT_SOC
UTO_OUT_PAR
UTO_OUT_CLK
Figure 21 - Overview of CBR Data Segmentation Process (UDT Mode)
MT90520
UTOPIA Module
UTOPIA
FIFO
TX
Zarlink Semiconductor Inc.
MT90520
59
UDT Segmentation
Control Structure
internal memory)
(one per port in
TX_SAR
Module (one per
TDM Interface
Buffer
Input
TDM
port)
Data Sheet
DSTi
LOSi
STiCLK
.