MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 37

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT90520
Data Sheet
4. Write other MT90520 registers. (Note that configuration bits must generally be programmed before setting pro-
cess enable bits.)
4.1.2
CPU Interrupts
The CPU interrupt mechanism works in a common way for all modules. Each module of the MT90520 has a status
register and a service request enable register. One or more additional status-related registers may also be located
within a module’s address space.
When a status bit is asserted, the corresponding service enable bit is checked. If the bit is set, the module’s service
request will be raised. The service request of the module will be asserted and stay high as long as any one of the
status/service enable pairs remains asserted.
This module’s service request is sent to the device’s Main Status Register (0002h). Within the microprocessor
block, there is an Interrupt Enable Register, located at byte address 000Ah. If any of the individual module service
requests is high, the corresponding interrupt enable bit is checked. If the appropriate interrupt enable bit is set, the
CPU module generates a global interrupt by driving the IRQ pin low. Note that the IRQ pin is tristated when there is
no active interrupt source. Refer to Figure 7 for an example of how an interrupt is generated within the MT90520.
Note that some of the modules within the MT90520 feature an additional level of interrupt masking. The memory-
and register-based interrupt mechanisms for these modules (UDT RX_SAR, SDT RX_SAR, and TDM) are
explained in the module descriptions for the blocks later in this document.
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