MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 54

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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If external memory is present in the system configuration containing the MT90520, any received cells whose
headers do not match those in the UDT search registers are passed to the look-up table sub-module and are
processed as detailed in the SDT Operation section that follows. This additional processing is provided primarily to
permit the reception of non-CBR data cells, and for additional OAM-cells (cells with VCI = 3h or VCI = 4h). This
extra processing also allows the user to process both SDT and UDT cells simultaneously. If no external memory is
present, the cells with unmatched headers (after passing through the VPI/VCI comparison registers) are simply
discarded.
SDT Operation
In the SDT case, the destination of the received cell is determined using a user-programmed look-up table. Unlike
the UDT case, all 28 bits of the header are not used to perform the look-up. Rather, a VPI/VCI concatenation
register (4002h) is provided for the user to choose how many bits of the cell header are to be used to form the look-
up table addresses. The user selects up to 16 of the bits of the combined GFC/VPI and VCI fields to be used for the
look-up table search. The look-up table itself is located in external memory, with each entry occupying one 16-bit
word. As such, the external memory requirement for this structure is 2
Each successful look-up search provides two pieces of information:
Refer to Figure 17 for the structure of a look-up table entry.
Depending on the value of the DS field of a look-up table entry, the UTOPIA module can process the cell in one of
the following ways:
module sends the cell to the Data RX_SAR. The Data RX_SAR (if enabled) is responsible for copying the
cell into the Receive Data Cell Buffer in external memory.
If the cell is carrying OAM data but the user has selected not to process OAM cells for that port (i.e.,
‘OAM_SEL’ bit for port = 0), the UTOPIA module discards the cell.
If the cell is not carrying OAM data, the UTOPIA module sends the cell to the UDT RX_SAR for processing.
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(M bits)
{LUTBASE, VPI<M-1:0>, VCI<N-1:0>, ‘0’}
minimum: 2
maximum: 2
the destination of the received cell (e.g., TDM bus, Receive Data Cell Buffer)
the address of the SDT Reassembly Control Structure associated with this VC (this field is ignored when
the received cell is not a CBR-type cell).
VPI
(N bits)
VCI
4
16
words (must use at least 4 bits from VCI field) = 16 words
{LUTBASE, “0 ... 0”}
BYTE ADDR. (hex)
words (can use at most 16 bits from combined header fields) = 64 Kwords
15
Reassembly Control
Reassembly Control
Reassembly Control
Reassembly Control
Reassembly Control
Reassembly Control
Structure Address
Structure Address
Structure Address
Structure Address
Structure Address
Structure Address
Figure 17 - Look-up Table Format
Zarlink Semiconductor Inc.
MT90520
54
6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
O
O
O
O
O
O
2
DS
DS
DS
DS
DS
DS
(VPI_bits + VCI_bits)
0
Reassembly Control Structure Address:
Represents bits<13:4> of the word address of
the SDT Reassembly Control Structure in inter-
nal memory.
Reserved: Unused (clear to all zeros)
O: Per-VCC OAM Select (‘0’ = OAM cell dis-
carded; ‘1’ = OAM cell placed in Receive Data
Cell Buffer in external memory).
DS: Destination of received cell (“00” =
unknown routing; “01” = TDM bus (i.e., SDT
RX_SAR); “10” = Receive Data Cell Buffer; “11”
= Discard)
LUTBASE: Portion of the LUT Base Address
Register (4004h) starting at bit<15> (represent-
ing MEM_ADD[20]) and ending at ULBA<M+N-
1> (where 4 < M+N < 16). M and N are deter-
mined by the UTOPIA Number of Concatenated
Bits Register (4002h).
words.
Data Sheet