MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 24

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

E4, D2, C1,
A2, B3, C3,
C4, A3, B4,
C5, A4, D6,
C6, D7, B6,
E7, B5, A5,
Ball Pin #
D3, D4
D5
A6
B1
C2
B2
A1
UTO_OUT_ADD[4
UTO_OUT_DATA[
UTO_OUT_ENBA
UTO_OUT_CLAV
UTO_OUT_SOC
UTO_OUT_CLK
UTO_OUT_PAR
ATM_ ENBPHY
TM_ CLAVPHY
Pin Name
15:0]
:0]
I/O
I/O 3.3 V CMOS
O
O
O
O
I
I
3.3 V CMOS
3.3 V, 12 mA 16-bit UTOPIA output data bus for cell-based data. When
3.3 V, 12 mA Odd parity bit over UTO_OUT_DATA[15:0]. When in 8-bit
3.3 V, 12 mA Start of Cell for UTO_OUT_DATA. Active HIGH output
3.3 V CMOS
3.3 V, 16 mA Handshake output for UTO_OUT_DATA.
PD / 24 mA
Table 4 - UTOPIA Bus Pins
Type
PD
PD
Zarlink Semiconductor Inc.
MT90520
Synchronization clock for data transfer on
This clock can be output from an internal divider (equal to
MCLK/2) or input from an external source. (TxClk when the
MT90520 is in ATM mode; RxClk when the MT90520 is in
PHY mode.)
Multi-PHY Address signals. These address inputs are used
to poll the MT90520, and to select the next MPHY device
to drive data on UTO_OUT_DATA. These signals are
driven from the ATM-end to the PHY-end, and only used
when the MT90520 is in PHY mode. (Inactive when the
MT90520 is in ATM mode; RxAddr when the MT90520 is in
PHY mode.)
in 8-bit mode, only bits [7:0] are active. In Level 2
operation, this bus is tristated between cell transmissions.
(TxData when the MT90520 is in ATM mode; RxData when
in PHY mode.)
mode, odd parity bit over UTO_OUT_DATA[7:0]. In Level 2
operation, this signal is tristated between cell
transmissions. (TxPrty when the MT90520 is in ATM mode;
RxPrty when in PHY mode.)
signal indicating the first word/byte of the cell being
transmitted. In Level 2 operation, this signal is tristated
between cell transmissions. (TxSOC when the MT90520 is
in ATM mode; RxSOC when in PHY mode.)
Handshake input for UTO_OUT_DATA.
When the MT90520 is in ATM mode, this input is TxClav,
indicating that the PHY-end can accept a complete cell on
UTO_OUT_DATA.
When the MT90520 is in PHY mode, this input is RxEnb*,
indicating that the ATM-end will begin to sample
UTO_OUT_DATA and UTO_OUT_SOC at the end of the
next clock cycle.
When the MT90520 is in ATM mode, this output is TxEnb*,
indicating that the data on UTO_OUT_DATA is valid.
When the MT90520 is in PHY mode, this output is RxClav,
indicating that the MT90520 has a complete cell ready to
output on UTO_OUT_DATA.
24
Description
UTO_OUT_DATA
Data Sheet
.