MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 142

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.2.9
Address: 6000 (Hex)
Label: MAINTDM1
Reset Value: FFFF (Hex)
Address: 6002 (Hex)
Label: MAINTDM2
Reset Value: F000(Hex)
SILENCE_DATA
Address: 6200 + p*10 (Hex)
Label: TDM1_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
TDM_LOS_POL
TDM_MAPPING_
TDM_CIR_BUF_
TDM_LOS_CLK
IDLE_DATA
IDLE_CAS
Reserved
TDM_CAS_
LOCATION
Label
Label
Label
LPBK
SCH
TDM Interface Module
Bit Position
Bit Position
15:12
Position
11:0
15:8
7:0
Bit
0
1
2
3
4
Table 82 - TDM Control Register 1 (one per port)
Type
R/W
Type
R/O
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 80 - Main TDM Control Register 1
Table 81 - Main TDM Control Register 2
Always reads “0000_0000_0000”.
User-programmable idle CAS. (Applies only to SDT mode.)
When a channel is idle (I bit is set in the corresponding TDM SDT Reassembly Control
Structure), idle CAS nibbles are output on CSTo.
TDM Circular Buffer Loopback. (Applies only to SDT mode.)
‘0’ = Normal operation.
‘1’ = Data input on DSTi is output on DSTo, after routing through the SDT circular buffers in
external memory.
Incoming Loss of Signal. (Applies only to UDT mode.)
‘0’ = Normal operation (continue to use STiCLK during an LOS condition).
‘1’ = Switch to MT90520’s internal clock source if loss of signal is detected on CSTi/LOSi.
Incoming TDM LOS Polarity. (Applies only to UDT mode; must be set in SDT mode.)
‘0’ = Negative polarity (i.e., zero on CSTi/LOSi means loss of signal).
‘1’ = Positive polarity (i.e., one on CSTi/LOSi means loss of signal).
TDM Signalling. (Applies only to SDT mode.)
‘0’ = Signalling nibbles are located in the LS four bits of each channel.
‘1’ = Signalling nibbles are located in the MS four bits of each channel.
TDM Mapping Scheme. (Applies only to an incoming DS1 link in SDT mode.)
In Generic mode:
‘0’ = Use first 24 channels.
‘1’ = Use 3 channels out of every 4.
In ST-BUS mode, this bit must be cleared.
User-programmable idle data. (Applies only to SDT mode.)
When a channel is idle (I bit is set in the corresponding TDM SDT Reassembly Control
Structure), idle data is output on DSTo.
User-programmable silence data. (Applies only to SDT mode.)
When a channel is experiencing a TDM underrun, this silence data is output on DSTo if
REPLAY_N_SILENCE is cleared in the TDM Control Register 3 for that port.
Zarlink Semiconductor Inc.
MT90520
142
Description
Description
Description
Data Sheet