MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 152

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address Setup - (AEM and CPU_ADD[20:1]
VALID) to (CS and WR asserted)
Address Hold - (CS or WR de-asserted) to
(AEM and CPU_ADD[20:1] INVALID)
RDY Low - CS asserted to RDY driven low
RDY Delay - (CS and WR asserted) to RDY
asserted
RDY High-Impedance - CS de-asserted to RDY
high-impedance
Write Cycle Hold Time - RDY asserted to (CS or
WR de-asserted)
Data Input Setup - CPU_DATA[15:0] VALID to
(CS and WR asserted)
Data Input Hold - (CS or WR de-asserted) to
CPU_DATA[15:0] INVALID
Note 1: MCLK = 66 MHz (15.2 ns)
Note 2: Both CS and WR must be asserted for a write cycle to occur. A write cycle is completed when either CS or WR is de-asserted.
Note 3: There should be a minimum of 3 MCLK periods between CPU accesses, to allow the MT90520 to recognize the accesses as
separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses).
CPU_DATA[15:0]
CPU_ADD[20:1]
AEM
Register access
Memory access
RDY
CS
WR
RD
Characteristic
t
t
WRDYL
ADDS
t
DS
Table 90 - Intel Microprocessor Interface Timing - Write Cycle Parameters
Figure 48 - Intel CPU Interface Timing - Write Access
t
t
WRDYL
t
WRDYZ
t
t
Sym.
WACC
t
ADDS
ADDH
ADDRESS VALID
WRH
t
t
DS
DH
Zarlink Semiconductor Inc.
DATA VALID
MT90520
t
WACC
Min.
167
182
0
0
0
0
0
0
0
152
Typ.
197
Max.
2021
213
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
C
C
11 MCLK < t
12 MCLK < t
C
WRH
L
L
L
= 75 pF
= 75 pF
= 75 pF
Test Conditions
t
t
WRDYZ
WACC
WACC
ADDH
t
DH
< 14 MCLK
< 133 MCLK
Data Sheet
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT