MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 86

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.6.1.6
The SDT RX_SAR and the UDT RX_SAR are responsible for generating data required for the performance of clock
recovery operations within the MT90520. In the case of adaptive clock recovery, the active RX_SAR must generate
a digital phaseword for transport to the internal per-port PLL. If SRTS clock recovery is being used, the RX_SAR
extracts 4-bit RTS values from incoming ATM cells and sends them to the corresponding port’s PLL.
Digital Phaseword Generation for Adaptive Clock Recovery
If the user has decided to use adaptive clock recovery to generate the TDM output clock, SToCLK, for a port, the A
(Adaptive Enable) bit in the UDT/SDT Reassembly Control Structure for the port must be set. In the UDT case,
there is only one VC per port. However, in the SDT case, only a single VC per port (where the port is identified by
the value in the VC TDM Port field of the Reassembly Control Structure) may have its A bit set. Note: In addition to
the Reassembly Control Structure, the PLL for the port must also be configured to operate in adaptive mode.
If the A bit is set, the UDT RX_SAR or the SDT RX_SAR is responsible for generating a digital phaseword for the
port’s PLL. These phasewords represent the fill level of the Reassembly Circular Buffer(s) for a port.
In UDT mode, if it is determined that a VC is cut (see Section 4.6.2.1 on page 87), no cells are being received at the
UDT RX_SAR. As a result, there is no frame of reference with which to adjust the output TDM clock rate.
Accordingly, the PLL is placed into holdover mode until cells are once again being received on the VC. At that point,
the output clock rate can be adjusted based on the buffer fill level.
For more information, see Section 4.7.2.6, “Adaptive Clock Recovery Circuit,” on page 102.
UTO_IN_ENBATM_CLAVPHY
UTO_IN_CLAVATM_ENBPHY
Clock Recovery Operations
UTO_IN_DATA[15:0]
UTO_IN_SOC
UTO_IN_PAR
UTO_IN_CLK
Figure 31 - Overview of CBR Data Reassembly Process (SDT Mode)
MT90520
UTOPIA Module
VC Look-Up
Table
UTOPIA
FIFO
TX
Zarlink Semiconductor Inc.
MT90520
Circular Buffers (one
86
per TDM channel)
SDT Reassembly
SDT Reassembly
Control Structure
internal memory)
(one per VC in
RX_SAR
SDT
Structure (one per port
External ZBT SRAM
Reassembly Control
in internal memory)
Module (one per
TDM Interface
Output
Buffer
TDM
TDM SDT
port)
Data Sheet
DSTo
CSTo
SToCLK
SToMF
.