MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 165

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.2.4.2
This section contains the timing diagrams for the MT90520 setup in UTOPIA Level 2 as a PHY device. For
functional timing diagrams, refer to the ATM Forum Level 2 specification (af-phy-0039.000).
Since the MT90520 does not support multi-PHY (MPHY) operation in ATM mode, the Level 2 ATM timing diagrams
are identical to the ones for Level 1 operation, except that in Level 2, the MT90520 features a 16-bit data bus in
both the TX and RX directions and it supports up to 80 pF of load at 33 MHz and 40 pF at 52 MHz. Note that the
address bus is only used when in PHY mode.
.
UTO_IN_CLK Period
UTO_IN_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
(UTO_IN_CLAVATM_ENBPHY, UTO_IN_SOC
asserted and UTO_IN_DATA[15:0],
UTO_IN_ADDR[4:0] VALID) to UTO_IN_CLK
rising
Input Hold Time - UTO_IN_CLK rising to
(UTO_IN_DATA[15:0], UTO_IN_ADDR[4:0]
INVALID and UTO_IN_SOC,
UTO_IN_CLAVATM_ENBPHY de-asserted)
Output Delay - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY asserted
Output Hold Time - UTO_IN_CLK rising to
(UTO_IN_ENBATM_CLAVPHY change)
UTO_OUT_CLK
UTO_OUT_CLAVATM
_ENBPHY
UTO_OUT_SOC
UTO_OUT_DATA[7:0]
UTO_OUT_ENBATM
_CLAVPHY
Table 102 - UTOPIA Level 2 Interface Timing - PHY mode - Incoming Data (UTOPIA TX Bus)
Figure 64 - UTOPIA Level 1 Interface Timing - PHY Mode - Outgoing Data (UTOPIA RX Bus)
UTOPIA Level 2
Characteristic
t
URXD
t
URX1P
t
URXIS
t
UTX2H/L
t
t
t
t
Sym.
t
t
UTX2P
t
UTXIH
UTXIS
URXH
UTXD
UTXH
URXH
Zarlink Semiconductor Inc.
H1
MT90520
19.23
Min.
7.7
4
1
1
1
165
t
UTX2P
Typ.
/2
t
P47
Max.
URXIH
13.8
20.5
t
URX1H
Units
P48
ns
ns
ns
ns
ns
ns
ns
ns
t
URX1L
UTO_IN_CLK = 52 MHz
C
C
C
C
L
L
L
L
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
=40 pF; UTO_IN_CLK < 52 MHz
=80 pF; UTO_IN_CLK < 33 MHz
Test Conditions
Data Sheet
H1
V
V
V
V
V
TT
TT
TT
TT
TT