MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 97

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.7.2.3
This sub-module is implemented only once within the MT90520 device and is used by both the Transmit SRTS and
Receive SRTS processes. The required circuitry is shown in Figure 38.
The primary function of this sub-module is to create a divided-down network clock, fnxi, from a PHY rate clock
(19.44 MHz) which is obtained from an external pin. This sub-module generates a number of different clock rates in
accordance with the requirements of the SRTS patent and the CES specification.
When operating in UDT mode, only a single multiplexer is required for RTS generation and SRTS clock recovery.
Since all of the VCs contain the same amount of data, only one network clock rate is required. This rate is set out in
the CES specification, af-vtoa-0078.000, as 2.430 MHz.
TDM Bus
Figure 37 - Synchronous TDM Rate Clock Generated by External PLL User-Selectable References
Module
STiCLK7
STiCLK0
STiCLK1
Network Clock Divider Circuit
PLLCLK0
PLLCLK1
PLLCLK7
MT90520
Clock Management Module
TDM_CLK
(Synchronous Clock #2)
{(PRI_SEL[5]|PRI_LOS),PRI_SEL<4:0>}
TDM_CLK
Zarlink Semiconductor Inc.
MT90520
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SEC_SEL<5:0>
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16:2
Mux
16:2
Mux
97
SEC_REF
PRI_REF
(e.g., MT9042)
External PLL
E1 = 2.048 MHz (also used for
ST-BUS = 4.096 MHz
DS1 = 1.544 MHz
Clock Rates:
framed DS1)
Data Sheet