MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 23

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

G2, H4, G3,
G4, F3, E1,
H3, J4, G1,
F1, F2, H5,
E2, F4, D1,
L4, J1, J2,
Ball Pin #
J3, K4
M4
H2
E3
K5
K3
H1
UTO_IN_ADD[4:0]
UTO_IN_ENBATM
UTO_IN_DATA[15
UTO_IN_CLAVAT
UTO_IN_SOC
UTO_IN_CLK
UTO_IN_PAR
M_ ENBPHY
_ CLAVPHY
Pin Name
:0]
I/O
I/O 3.3 V CMOS
O
I
I
I
I
I
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V, 16 mA Handshake output for UTO_IN_DATA.
3.3 V CMOS
PD / 24 mA
Table 4 - UTOPIA Bus Pins
Type
PD
PD
PD
PD
PD
Zarlink Semiconductor Inc.
MT90520
Synchronization clock for data transfer on UTO_IN_DATA.
This clock can be output from an internal divider (equal to
MCLK/2) or input from an external source. (RxClk when
the MT90520 is in ATM mode; TxClk when the MT90520 is
in PHY mode.)
Multi-PHY address signals. These address inputs are used
to poll the MT90520 and to select the next MPHY device to
receive data on UTO_IN_DATA. These signals are driven
from the ATM-end to the PHY-end, and only used when the
MT90520 is in PHY mode. (Inactive when the MT90520 is
in ATM mode; TxAddr when the MT90520 is in PHY
mode.)
16-bit UTOPIA input bus for cell-based data. When in 8-bit
mode, only bits [7:0] are active. (RxData[15:0] when the
MT90520 is in ATM mode; TxData[15:0] when in PHY
mode.)
Odd parity bit over UTO_IN_DATA[15:0]. When in 8-bit
mode, odd parity bit over UTO_IN_DATA[7:0]. (RxPrty
when the MT90520 is in ATM mode; TxPrty when in PHY
mode.)
Start of Cell for UTO_IN_DATA. Active HIGH input signal
indicating the first word/byte of the cell being received.
(RxSOC when the MT90520 is in ATM mode; TxSOC when
in PHY mode.)
Handshake input for UTO_IN_DATA.
When the MT90520 is in ATM mode, this input is RxClav,
indicating that the PHY-end has a complete cell to transfer
on UTO_IN_DATA.
When the MT90520 is in PHY mode, this input is TxEnb*,
indicating that the ATM-end is transferring valid data on
UTO_IN_DATA.
When the MT90520 is in ATM mode, this output is RxEnb*,
indicating that the MT90520 will begin to sample
UTO_IN_DATA and UTO_IN_SOC at the end of the next
clock cycle.
When the MT90520 is in PHY mode, this output is TxClav,
indicating that the MT90520 can accept a complete cell on
UTO_IN_DATA.
23
Description
Data Sheet