MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 99

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.7.2.4
In the segmentation direction, the purpose of the transmit SRTS circuit sub-module is to generate 4-bit Residual
Time Stamps (RTSs) to be inserted within the headers of ATM cells output on the UTOPIA bus. In the reassembly
direction, this circuit is used to generate local RTS values which are compared (by an internal PLL) with the RTS
values extracted from received cells. Segmentation operation is explained in this section, but the reassembly
function is discussed in Section 4.7.2.5, “Receive SRTS Circuit Sub-Module”.
As outlined in U.S. Patent No. 5,260,978, in the segmentation direction, the transmit SRTS circuit compares the
local clock rate, determined by STiCLK for a particular port (in independent clocking or ST-BUS backplane mode) or
C4M/C2M (when operating in Generic backplane mode) with the output of an fnxi counter clocked by the Network
Clock Divider circuit examined in Section 4.7.2.3 on page 97. The result of the comparison is stored in a FIFO, for
eventual transmission of the RTS nibbles to the TX_SAR. Underrun and overflow detection are provided on the
Transmit SRTS FIFO via status bits in CPU-accessible registers. The circuit operates in essentially the same way in
the reassembly direction, except that the local clock rate is determined by the clock at the output of the port’s
internal PLL, PLLCLK. As well, in the reassembly direction, data is sent to the Receive SRTS sub-module rather
than being sent to the Transmit SRTS FIFO. Figure 39 shows how the circuit is implemented.
UDT Operation
The STiCLK or PLLCLK signal for each port (C4M/C2M isn’t used, because it is an SDT-mode signal) is divided
down to generate a clock, RTS_CLK. This clock has the same frequency as a cycle of RTS. Since one RTS value is
transmitted over the course of 8 cells, the division is by 3008, the number of payload bits transmitted within one
RTS period (8 cells containing 47 payload bytes). Every time RTS_CLK pulses, the current value of the appropriate
fnxi counter is stored in a FIFO. A value from the FIFO is transmitted to the TX_SAR cell header generator circuit
once every 8-cell sequence.
Note 2: PLLCLK is used when receiving RTS (clock recovery) or to dejitter the clock before generating RTS.
Note 1: The 4-bit fnxi counters are only required once per device. All the other circuitry is instantiated on a per-port basis.
C4M/C2M
PLLCLK
STiCLK
Transmit SRTS Circuit Sub-module
RTSSEL
Mux
Figure 40)
Circuitry
Gapping
sync_clk
(see
SDT/UDT
Mux
2:1
Divider Circuit)
Network Clock
fnxi counters
(generated by
Figure 39 - Transmit SRTS Sub-module
Clock Management Module
(/ 3008 or
SDT/UDT
Circuitry
Divider
/ 3000)
Zarlink Semiconductor Inc.
MT90520
fnxi2_count<3:0>
fnxi1_count<3:0>
99
To port’s PLL for RX
SRTS Recovery
Mux
2:1
RTS_int<3:0>
RTS_CLK
FNXISEL
4
New FIFO Entry
5-deep 4-bit
FIFO
4
Data Sheet
Transmit RTS
TX_SAR
Module
Value