MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 146

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.2.10
Address: 620A + p*10 (Hex)
Label: TDM6_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Address: 7000 (Hex)
Label: MACR
Reset Value: 0000 (Hex)
Address: 7004 (Hex)
Label: PERS
Reset Value: 0000 (Hex)
UNDERRUN_
LBPRTY_E
Reserved
REPORT
PERM_
MCFG
MTYP
PESE
Label
Label
Label
External Memory Interface Module
Position
Position
Position
15:5
Bit
2:0
Bit
15:0
3
4
0
Bit
Table 88 - Memory Arbiter Configuration Register
Table 87 - TDM Control Register 6 (one per port)
R/O/L
Type
Type
R/O/L
R/W
R/W
R/W
R/O
Type
Table 89 - Parity Error Status Register
Memory Configuration:
“000” = No external memory
“100” = Bank of 1 M words (max. 1 bank)
“101” = Banks of 512 K words (max. 2 banks)
“110” = Banks of 256 K words (max. 4 banks)
“111” = Banks of 128 K words (max. 4 banks)
All others = Reserved.
Memory Type:
‘0’ = Flow-through
‘1’ = Pipelined.
Parity Error Service Enable.
When this bit is set and either the LPPRTY_E bit or the HBPRTY_E bit is asserted at
7004h, the XMEMA_SRV bit is set in the Main Status Register at 0002h.
Always reads “0000_0000_000”.
Low Byte Parity Error.
If set, this bit indicates that a parity error has occurred in the lower 8 bits of the data word
being read from external memory. A parity error may occur if a location in memory is read
before being written. Writing ‘0’ to this bit clears it.
Permanent Underrun Report. (Applies only to SDT mode.)
This register represents bits<15:0> of the 32-bit permanent underrun reports. Bit<15>
corresponds to channel 15, bit<14> corresponds to channel 14, etc.
When an underrun occurs on a certain channel, the corresponding bit is set high; the
microprocessor can clear these bits by writing them to ‘0’.
Zarlink Semiconductor Inc.
MT90520
146
Description
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Description
Data Sheet