MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 121

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 1038 (Hex)
Label: DTCON
Reset Value: 0000 (Hex)
Address: 103A (Hex)
Label: DTWPR
Reset Value: 0000 (Hex)
Address: 103C (Hex)
Label: DTRPR
Reset Value: 0000 (Hex)
Reserved
Reserved
Reserved
DTBASE
DTSIZE
DTWP
DTRP
Label
Label
Label
Position
Position
Position
15:10
15:8
15:7
1:0
9:2
7:0
6:0
Bit
Bit
Bit
Table 34 - Data TX_SAR Configuration Register
Table 35 - Data TX_SAR Write Pointer Register
Table 36 - Data TX_SAR Read Pointer Register
Type
Type
Type
R/W
R/W
R/W
R/O
R/O
R/O
R/O
Data TX_SAR Cell Buffer Size.
This field indicates the number of non-CBR data cells which can be held in the Data
TX_SAR’s Cell Buffer:
“00” = 16 cells
“01” = 32 cells
“10” = 64 cells
“11” = 128 cells.
Data TX_SAR Cell Buffer Base Address.
These bits represent address bits<19:12> of the base address (in words) of the cell buffer
in external memory.
Always reads “0000_00”.
Data TX_SAR Write Pointer.
Indicates the cell structure number to which the CPU is currently writing (the cell is not yet
valid).
Always reads “0000_0000”.
Data TX_SAR Read Pointer.
Indicates the cell structure number from which the Data TX_SAR is currently reading. This
pointer is cleared when the TDSENB bit in the Data TX_SAR Control Register at 103Eh is
cleared.
Always reads “0000_0000_0”.
Zarlink Semiconductor Inc.
MT90520
121
Description
Description
Description
Data Sheet