MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 171

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Figure 69 illustrates the connections from the external pins of the UTOPIA interface to an ATM device, when the
MT90520 device is operating in PHY mode.
ATM Device
Note 1: The ATM device is not required to drive the UTOPIA clock. The UTO_IN_CLK and UTO_OUT_CLK pins of
the MT90520 can either be inputs or outputs.
Note 2: When in PHY mode, UTO_IN_ENBATM_CLAVPHY, UTO_IN_SOC, UTO_OUT_ENBATM_CLAVPHY and
UTO_OUT_SOC should be pulled down. It is also recommended to pull up UTO_IN_CLAVATM_ENBPHY and
UTO_OUT_CLAVATM_ENBPHY.
RxData[15:0]
TxData[15:0]
RxAddr[4:0]
TxAddr[4:0]
RxEnb*
RxSOC
TxEnb*
TxSOC
RxClav
TxClav
TxPrty
RxPrty
RxClk
TxClk
Figure 69 - PHY Mode: External UTOPIA Pin Connections
UTO_IN_PAR
UTO_OUT_CLK
UTO_OUT_CLAVATM_ENBPHY
UTO_OUT_ENBATM_CLAVPHY
UTO_OUT_DATA[15:0]
UTO_OUT_SOC
UTO_OUT_ADD[4:0]
UTO_OUT_PAR
UTO_IN_CLK
UTO_IN_CLAVATM_ENBPHY
UTO_IN_ENBATM_CLAVPHY
UTO_IN_DATA[15:0]
UTO_IN_SOC
UTO_IN_ADD[4:0]
Zarlink Semiconductor Inc.
MT90520
171
RX UTOPIA
TX UTOPIA
RX Parity
TX Parity
Interface
Interface
MT90520
Mode)
(PHY
Data Sheet