MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 20

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Ball Pin #
D24, C26,
B21, D20,
C21, A22,
B22, D21,
A23, C22,
D22, B23,
A24, C23,
D23, B24,
A25, A26,
B26, C24,
D25, E23,
E24, D26,
G22, F23,
E25, E26,
G23, F25,
F26, G24,
H23, G25
B25, C25
J22, F24,
G26
H26
H25
H24
J23
MEM_ADD[19:0
MEM_DATA[17:
MEM_CS_1
MEM_CS_2
MEM_CS_3
MEM_CS_4
Pin Name
MEM_WR
0]
]
I/O
I/O 3.3 V CMOS
Table 2 - External Memory Interface Pins
O
O
O
O
O
O
3.3 V, 8 mA Active LOW memory chip select signal for bank 1. This
3.3 V, 8 mA Active LOW memory chip select signal for bank 2. This
3.3 V, 8 mA Active LOW memory chip select signal for bank 3. This
3.3 V, 8 mA Active LOW memory chip select signal for bank 4. This
3.3 V, 8 mA Active LOW write enable.
3.3 V, 8 mA Memory address lines. Connect these lines to external
PD / 8 mA
Type
Zarlink Semiconductor Inc.
MT90520
signal is used in all memory configurations to select bank 1
of external memory.
signal is used to enable memory bank 2 when 2 or more
banks of external RAM are connected to the MT90520.
signal is used to enable memory bank 3 when 4 banks of
external RAM are connected to the MT90520.
signal is used to enable memory bank 4 when 4 banks of
external RAM are connected to the MT90520.
memory as follows:
Bank Size of 1 M: MEM_ADD[19:0] are connected to
memory.
Bank Size of 512 K: MEM_ADD[18:0] are connected to
memory.
Bank Size of 256 K: MEM_ADD[17:0] are connected to
memory.
Bank Size of 128 K: MEM_ADD[16:0] are connected to
memory.
Memory data lines. MEM_DATA[15:8] represent the upper
byte; MEM_DATA[7:0] represent the lower byte. Optional
lines [17] and [16] represent the high and low byte parity
values, respectively.
20
Description
Data Sheet