MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 78
![no-image](/images/no-image-200.jpg)
MT90520AG
Manufacturer Part Number
MT90520AG
Description
8-Port Primary Rate Circuit Emulation AAL1 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90520AG.pdf
(180 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 78 of 180
- Download datasheet (2Mb)
MT90520
Data Sheet
UDT Mode of Operation
In “normal” operation (i.e., the UDT RX_SAR’s Fast SN Processing state machine is in “sync”), the UDT RX_SAR is
responsible for transferring a UDT cell received at the UTOPIA interface to a single UDT Reassembly Circular
Buffer in internal memory (corresponding to the TDM port for which the data is destined). However, if it is not in
“sync”, the UDT RX_SAR may also be responsible for inserting up to 7 dummy cells (each filled with 47 bytes of
user-defined data) into the port’s UDT Reassembly Circular Buffer.
Regardless of the state of the Fast SN Processing state machine, a comparison is made between the value of the
UDT RX_SAR’s write pointer and the TDM module’s read pointer, prior to the transfer of each cell to the circular
buffer. The result of the comparison determines whether a slip-error needs to be reported in the MIB statistics, and
may also result in an adjustment of the write pointer’s location before a cell is written to the UDT Reassembly
Circular Buffer (see UDT Overflow and Underrun Detection below).
TDM Data Transfer
Normally the UDT RX_SAR simply transfers 47-byte blocks of data from the UTOPIA interface to a port’s UDT
Reassembly Circular Buffer. However, in the case of a cell loss or misinsertion, up to 7 dummy cells may be
inserted into the circular buffer before the received cell is accepted. If the user has set the UDT_INSERT_LOST bit
in the UDT Reassembly Control Register at byte-address 2000h, the UDT RX_SAR is configured to insert the
number of dummy cells calculated by the Fast SN Processing state machine in a cell loss case. On the other hand,
if the user has not set the UDT_INSERT_LOST bit, the UDT RX_SAR will insert a maximum of 2 dummy cells (i.e.,
even if the number of lost cells is greater than 2, only 2 dummy cells may be inserted) into the UDT Reassembly
Circular Buffer in a cell-loss event.
UDT Reassembly Circular Buffers
In the UDT mode of operation, each VC has a specified UDT Reassembly Circular Buffer located in internal
memory. Each buffer is 2048 bytes long and is therefore capable of storing over 43 cells worth of data. The user
can adjust the Maximum Lead field in the VC’s UDT Reassembly Control Structure to control the CDV tolerance of
the VC. The Maximum Lead field, as explained in Section , “UDT Reassembly Control Structures,” on page 67, is
user-programmable and determines the maximum distance between the TDM module’s read pointer and the UDT
RX_SAR’s write pointer. In general, the operations of the UDT RX_SAR and the TDM module are synchronized so
that the UDT RX_SAR’s write pointer and the TDM module’s read pointer are always an average distance
(equivalent to Maximum Lead / 2) apart. This phenomenon occurs because most of the time, each time that the
UDT RX_SAR writes a complete cell to the circular buffer, the TDM module reads the complete cell (1:1
relationship).
UDT Overflow and Underrun Detection
The UDT RX_SAR is responsible for generating buffer overflow and buffer underrun error notifications on a per-VC
basis. In addition to determining if errors occur, the UDT RX_SAR also attempts to compensate for these slips by
adjusting its write pointer. The goal of the write pointer adjustment is to prevent the occurrence of subsequent slips.
When the first cell is about to be written to the UDT Reassembly Circular Buffer for a VC, the UDT RX_SAR looks
at the current value of the TDM read pointer and adjusts the value of its write pointer to be equal to TDM read
pointer + avg_lead (where avg_lead is equal to Maximum_Lead / 2). Therefore, if no slips occur, the write pointer
should always be an “average” distance away from the TDM read pointer.
For all subsequent cells, an algorithmic slip-checking routine is performed for every cell which is written to the UDT
Reassembly Circular Buffer, whether it is a dummy cell or a received ATM cell. Each time a cell is to be written to
internal memory, the algorithm looks at the relationship between the UDT RX_SAR’s write pointer and the TDM
module’s read pointer. The algorithm then determines whether the next write to occur will be an “okay” condition, an
overflow, or an underrun. Generally speaking, an “okay” condition means that the UDT RX_SAR is trying to write to
a memory location which is within a distance of Maximum Lead from the TDM read pointer. Overflow conditions are
conditions in which there is a risk of the UDT RX_SAR over-writing data which has yet to be read by the TDM
78
Zarlink Semiconductor Inc.
Related parts for MT90520AG
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![SL1430](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_tmb.jpg)
Part Number:
Description:
Zarlink Semiconductor Inc [TV IF PREAMPLIFIER]
Manufacturer:
Zarlink Semiconductor
Datasheet:
![MT312C](/images/no-image3.png)
Part Number:
Description:
Satellite Channel Decoder
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![MSC60028/IG/DP2S](/images/no-image3.png)
Part Number:
Description:
Power Factor Controller
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![P10C68-](/images/no-image3.png)
Part Number:
Description:
CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL2009KG](/images/no-image3.png)
Part Number:
Description:
Dual stage IF amplifier for cable tuners
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL2101C](/images/no-image3.png)
Part Number:
Description:
Synthesized Broadband Converter with Programmable Power
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL2150KG](/images/no-image3.png)
Part Number:
Description:
Cable Tuner Front End LNA with AGC
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL2150LH2S](/images/no-image3.png)
Part Number:
Description:
Front End Power Splitter with AGC
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL2524HP](/images/no-image3.png)
Part Number:
Description:
1.3GHz Dual Wideband Logarithmic Amplifier
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL2610IG](/images/no-image3.png)
Part Number:
Description:
Wide Dynamic Range Image Reject MOPLL
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL1451NADP](/images/no-image3.png)
Part Number:
Description:
WIDEBAND PLL FM DETECTOR FOR SATELLITE TV
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL1452NAMP](/images/no-image3.png)
Part Number:
Description:
WIDEBAND LINEAR FM DETECTOR FOR SATELLITE TV
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL161](/images/no-image3.png)
Part Number:
Description:
WIDEBAND LOG IF STRIP AMPLIFIER
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL1613CDP](/images/no-image3.png)
Part Number:
Description:
WIDEBAND LOG IF STRIP AMPLIFIER
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
![SL1640](/images/no-image3.png)
Part Number:
Description:
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet: