MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet - Page 62

• Manufacturer Part Number: MT90520AG
• Description: 8-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The per-port TX_SAR Pointer Table Base Registers (at byte addresses 1000h + p*2h) must be configured to point
to the SDT Segmentation Pointer Tables for their respective ports. As well, the TXCFG bits in the register must be
set to “11”, indicating that the control structures being pointed to by the table are configured for SDT mode.
Once the control structures and accompanying pointer tables have been configured, the transmission of CBR cells
can begin as soon as the TX_SAR is enabled, by setting the TXENB bit in the TX_SAR Master Enable Register at
byte address 1044h.
4.5.3.3
In SDT mode, once the SDT Segmentation Control Structure has been configured and the TX_SAR enabled, the
TX_SAR begins to generate cells with the appropriate formatting, without further software intervention. The
TX_SAR reads data (consisting of TDM data bytes and, where appropriate, CAS signalling bytes) from the per-
channel SDT Segmentation Circular Buffers in external memory. Refer to Section and Figure 11, “Per-Port SDT
Segmentation Circular Buffers,” on page 43 for details regarding the formatting of the data which is written to these
circular buffers by the TDM module. The TX_SAR prepends the TDM data with an AAL1 sequence number and
with a 6-byte header as specified by the VC’s SDT Segmentation Control Structure. Additionally, as defined in the
AAL1 specifications, one even-numbered cell out of each eight-cell sequence contains a pointer byte. The TX_SAR
uses internal counters to determine the appropriate value for the pointer byte, which indicates the start of the next
structure within the outgoing cell stream on a VC.
Figure 24 shows the complete segmentation data path in SDT mode, from the incoming TDM data bus to the
outgoing UTOPIA data bus.
15
Note: SDT Segmentation Pointer Tables must
start on 32-word (64-byte) boundaries.
L E
L E
L E
14
13
12
Control Structure 31 Base Address
Operation
Control Structure 1 Base Address
Control Structure 0 Base Address
11
10
9
8
7
6
5
4
3
Figure 23 - SDT Segmentation Pointer Table for Port p
2
1
0
Zarlink Semiconductor Inc.
L (Last Valid Pointer): When set, indicates that the current pointer is the last valid
pointer in the table.
E (Enabled): When set, indicates that the corresponding Segmentation Control
Structure is enabled.
Control Structure X Base Address: This field specifies the location of the Segmen-
tation Control Structures for one of the VCs associated with port p. The word address
is an offset relative to the base address of the TX_SAR Control Memory (address
80000h).
MT90520
TXPTB_Pp Register<13:0>
62
Data Sheet