OM11077 NXP Semiconductors, OM11077 Datasheet - Page 204

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
Writing to the IOPIN register stores the value in the port output register, bypassing the
need to use both the IOSET and IOCLR registers to obtain the entire written value. This
feature should be used carefully in an application since it affects the entire port.
Legacy registers are the IO0PIN and IO1PIN while the enhanced GPIOs are supported
via the FIO0PIN, FIO1PIN, FIO2PIN, FIO3PIN and FIO4PIN registers. Access to a port
pin via the FIOPIN register is conditioned by the corresponding bit of the FIOMASK
register (see
FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF
Only pins masked with zeros in the Mask register (see
Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF
correlated to the current content of the Fast GPIO port pin value register.
Table 170. GPIO port Pin value register (IO0PIN - address 0xE002 8000 and IO1PIN - address
Table 171. Fast GPIO port Pin value register (FIO[0/1/2/3/4]PIN - address
Aside from the 32-bit long and word only accessible FIOPIN register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table
additional registers allow easier and faster access to the physical port pins.
Bit
31:0
Bit
31:0
10–172, too. Next to providing the same functions as the FIOPIN register, these
Symbol
P0xVAL
or
P1xVAL
Symbol
FP0xVAL
FP1xVAL
FP2xVAL
FP3xVAL
FP4xVAL
0xE002 8010) bit description
0x3FFF C0[1/3/5/7/9]4) bit description
Section 10–6.5 “Fast GPIO port Mask register
Value Description
0
1
Value Description
0
1
Rev. 04 — 26 August 2009
Slow GPIO pin value bits. Bit 0 in IOxPIN corresponds to pin
Px.0, bit 31 in IOxPIN corresponds to pin Px.31.
Controlled pin output is set to LOW.
Controlled pin output is set to HIGH.
Fast GPIO output value Set bits. Bit 0 in FIOxCLR corresponds
to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31.
Controlled pin output is set to LOW.
Controlled pin output is set to HIGH.
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
C0[1/3/5/7/9]0)”).
Section 10–6.5 “Fast GPIO port
C0[1/3/5/7/9]0)”) will be
UM10237
© NXP B.V. 2009. All rights reserved.
204 of 792
Reset
value
0x0
Reset
value
0x0