OM11077 NXP Semiconductors, OM11077 Datasheet - Page 37

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
Masters with the same priority value are scheduled on a round-robin basis.
Table 35.
[1]
Bit
0
2:1
3
7:4
9:8
11:10 -
13:12 EP1
15:14 -
17:16 EP2
31:18 -
Allowed values for nn are: 10 (high priority) and 01 (low priority).
Symbol
scheduler
break_burst
quantum_type
quantum_size
default_master
AHB Arbiter Configuration register 2 (AHBCFG2 - address 0xE01F C18C) bit
description
Rev. 04 — 26 August 2009
Value Description
0
1
00
01
10
11
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
nn
-
nn
-
nn
-
Break all defined length bursts (the CPU does not create
Master 2 (Ethernet) is the default master.
Priority scheduling.
Uniform (round-robin) scheduling.
defined bursts).
Break all defined length bursts greater than four-beat.
Break all defined length bursts greater than eight-beat.
Never break defined length bursts.
A quantum is an AHB clock.
A quantum is an AHB bus cycle.
Controls the type of arbitration and the number of quanta
before re-arbiration occurs.
Preemptive, re-arbitrate after 1 AHB quantum.
Preemptive, re-arbitrate after 2 AHB quanta.
Preemptive, re-arbitrate after 4 AHB quanta.
Preemptive, re-arbitrate after 8 AHB quanta.
Preemptive, re-arbitrate after 16 AHB quanta.
Preemptive, re-arbitrate after 32 AHB quanta.
Preemptive, re-arbitrate after 64 AHB quanta.
Preemptive, re-arbitrate after 128 AHB quanta.
Preemptive, re-arbitrate after 256 AHB quanta.
Preemptive, re-arbitrate after 512 AHB quanta.
Preemptive, re-arbitrate after 1024 AHB quanta.
Preemptive, re-arbitrate after 2048 AHB quanta.
Preemptive, re-arbitrate after 4096 AHB quanta.
Preemptive, re-arbitrate after 8192 AHB quanta.
Preemptive, re-arbitrate after 16384 AHB quanta.
Non- preemptive, infinite AHB quanta.
Reserved.
External priority for master 1 (CPU).
Reserved.
External priority for master 2 (Ethernet).
Reserved. User software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Chapter 3: LPC24XX System control
UM10237
© NXP B.V. 2009. All rights reserved.
37 of 792
Reset
value
1
10
0100
01
-
00
-
NA
0
00