OM11077 NXP Semiconductors, OM11077 Datasheet - Page 650

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.2.1 Interrupt Location Register (ILR - 0xE002 4000)
6.1 RTC interrupts
6.2 Miscellaneous register group
Table 566. Summary of Real-Time Clock registers
[1]
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the
time counters. If CIIR is enabled for a particular counter, then every time the counter is
incremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm
compares. If all nonmasked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of Power-down and Deep power-down
mode if the RTC is operating from its own oscillator on the RTCX1-2 pins. When the RTC
interrupt is enabled for wakeup and its selected event occurs, the oscillator wakeup cycle
associated with the XTAL1/2 pins is started. For details on the RTC based wakeup
process see
page 63
The Interrupt Location Register specifies which blocks are generating an interrupt (see
Table
Writing a zero has no effect. This allows the programmer to read this register and write
back the same value to clear only the interrupt that is detected by the read.
Table 567. Interrupt Location Register (ILR - address 0xE002 4000) bit description
Name
ALYEAR
PREINT
PREFRAC
Bit
0
1
2
7:2
Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset. These
registers must be initialized by software if the RTC is enabled. Reset Value reflects the data stored in used
bits only. It does not include reserved bits content.
26–567). Writing a one to the appropriate bit clears the corresponding interrupt.
Symbol
RTCCIF
RTCALF When one, the alarm registers generated an interrupt. Writing a one to
RTSSF
-
and
Description
Alarm value for Year
Prescaler value, integer portion
Prescaler value, fractional portion
Section 4–3.4.8 “Interrupt Wakeup Register (INTWAKE - 0xE01F C144)” on
Section 4–5 “Wakeup timer” on page
Description
When one, the Counter Increment Interrupt block generated an interrupt.
Writing a one to this bit location clears the counter increment interrupt.
this bit location clears the alarm interrupt.
When one, the Counter Increment Sub-Seconds interrupt is generated.
The interrupt rate is determined by the CISS register.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
…continued
67.
Access
R/W
R/W
R/W
Reset
Value
NC
0
0
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE002 407C
0xE002 4080
0xE002 4084
650 of 792
Reset
value
NC
NC
NC
NA