OM11077 NXP Semiconductors, OM11077 Datasheet - Page 616

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
5.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)
5.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)
5.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)
Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in
chapter for details of DMA operation.
Table 537: DMA Configuration register 1 (I2SDMA1 - address 0xE008 8014) bit description
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in
Table 538: DMA Configuration register 2 (I2SDMA2 - address 0xE008 8018) bit description
The I2SIRQ register controls the operation of the I
in I2SIRQ are shown in
Bit
15:8
23:16 tx_level
31:24 -
Bit
0
1
7:2
15:8
23:16
31:24
Bit
0
1
7:2
15:8
23:16
31:24
Symbol
rx_level
Symbol
rx_dma2_enable
tx_dma2_enable
Unused
rx_depth_dma2
tx_depth_dma2
-
Symbol
rx_dma1_enable
tx_dma1_enable
Unused
rx_depth_dma1
tx_depth_dma1
-
Description
Reflects the current level of the Receive FIFO.
Reflects the current level of the Transmit FIFO.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Table
Table
Table
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request on
DMA1.
Set the FIFO level that triggers a transmit DMA request on
DMA1.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request
on DMA2.
Set the FIFO level that triggers a transmit DMA request
on DMA2.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
23–537. Refer to the General Purpose DMA Controller
23–532.
23–532.
2
S interrupt request. The function of bits
Chapter 23: LPC24XX I
2
2
S receive.
S transmit.
2
2
S receive.
S transmit.
UM10237
© NXP B.V. 2009. All rights reserved.
2
S interface
Reset
Value
0
0
0
0
0
NA
616 of 792
0
0
Reset
Value
NA
Reset
Value
0
0
0
0
0
NA