OM11077 NXP Semiconductors, OM11077 Datasheet - Page 344

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 308. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit description
UM10237_4
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
EP0RX
EP0TX
EP1RX
EP1TX
EP2RX
EP2TX
EP3RX
EP3TX
EP4RX
EP4TX
EP5RX
EP5TX
EP6RX
EP6TX
EP7RX
EP7TX
EP8RX
EP8TX
EP9RX
EP9TX
EP10RX
EP10TX
EP11RX
EP11TX
EP12RX
EP12TX
EP13RX
EP13TX
EP14RX
EP14TX
EP15RX
EP15TX
9.4.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0xFFE0 C234)
Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 2, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 3, Isochronous endpoint.
Endpoint 4, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 5, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 6, Isochronous endpoint.
Endpoint 7, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 8, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 9, Isochronous endpoint.
Endpoint 10, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 11, Data Received Interrupt bit.
Endpoint 11, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 12, Isochronous endpoint.
Endpoint 13, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 14, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 15, Data Transmitted Interrupt bit or sent a NAK.
Description
Endpoint 0, Data Received Interrupt bit.
Endpoint 1, Data Received Interrupt bit.
Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 2, Data Received Interrupt bit.
Endpoint 3, Isochronous endpoint.
Endpoint 4, Data Received Interrupt bit.
Endpoint 5, Data Received Interrupt bit.
Endpoint 6, Isochronous endpoint.
Endpoint 7, Data Received Interrupt bit.
Endpoint 8, Data Received Interrupt bit.
Endpoint 9, Isochronous endpoint.
Endpoint 10, Data Received Interrupt bit.
Endpoint 12, Isochronous endpoint.
Endpoint 13, Data Received Interrupt bit.
Endpoint 14, Data Received Interrupt bit.
Endpoint 15, Data Received Interrupt bit.
Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set
when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the
corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated
endpoint. USBEpIntEn is a read/write register.
Rev. 04 — 26 August 2009
Chapter 13: LPC24XX USB device controller
UM10237
© NXP B.V. 2009. All rights reserved.
Reset value
0
0
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
0
0
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