OM11077 NXP Semiconductors, OM11077 Datasheet - Page 311

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.8 LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
The contents of the LCD_LPBASE register are described in
Table 266. Lower Panel Frame Base register (LCD_LPBASE, RW - 0xFFE1 0014)
The LCD_CTRL register controls the LCD operating mode and the panel pixel
parameters.
The contents of the LCD_CTRL register are described in
Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
Bits
31:3
2:0
Bits
31:17
16
15:14
13:12
11
Function
LCDLPBASE
reserved
Function
reserved
WATERMARK LCD DMA FIFO watermark level.
reserved
LcdVComp
LcdPwr
Rev. 04 — 26 August 2009
Description
LCD lower panel base address.
This is the start address of the lower panel frame data in memory
and is doubleword aligned.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Controls when DMA requests are generated:
0 = An LCD DMA request is generated when either of the DMA
FIFOs have four or more empty locations.
1 = An LCD DMA request is generated when either of the DMA
FIFOs have eight or more empty locations.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD Vertical Compare Interrupt.
Generate VComp interrupt at:
00 = start of vertical synchronization.
01 = start of back porch.
10 = start of active video.
11 = start of front porch.
LCD power enable.
0 = power not gated through to LCD panel and LCDV[23:0]
signals disabled, (held LOW).
1 = power gated through to LCD panel and LCDV[23:0] signals
enabled, (active).
See LCD power-up and power-down sequence for details on
LCD power sequencing.
Chapter 12: LPC24XX LCD controller
Table
Table
12–267.
12–266.
UM10237
© NXP B.V. 2009. All rights reserved.
311 of 792
Reset
value
0x0
-
Reset
value
-
0x0
-
0x0
0x0