OM11077 NXP Semiconductors, OM11077 Datasheet - Page 47

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
Fig 14. PLL block diagram (N = 16, M = 125, USBSEL = 6, CCLKSEL = 4)
pllclkin =
18.432 MHz
PLLC
PLLE
NSEL[23:16]
MSEL[14:0]
pd
3.2.1 PLL operation
N-DIVIDER
The PLL input, in the range of 32 kHZ to 24 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. The multiplier can multiply the input
divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in
the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
There are additional dividers at the PLL output to bring the frequency down to what is
needed for the CPU, USB, and other peripherals. The PLL output dividers are described
in the Clock Dividers section following the PLL description. A block diagram of the PLL is
shown in
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider
values are controlled by the PLLCFG register. These two registers are protected in order
to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all
chip operations, including the Watchdog Timer, could be dependent on the PLL if so
configured (for example when it is providing the chip clock), accidental changes to the PLL
setup could result in unexpected or fatal behavior of the microcontroller. The protection is
accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLLFEED register.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only.
It is important that the setup procedure described in
sequence”
/16
1.152 MHz
Figure 4–14
is followed as is or the PLL might not operate at all!.
refclk =
1.152 MHz
M-DIVIDER
FREQUENCY
DETECTOR
/125
PHASE-
Rev. 04 — 26 August 2009
PLOCK
144 MHz
FILTER
/2
Chapter 4: LPC24XX Clocking and power control
288 MHz
CCO
288
MHz
Section 4–3.2.14 “PLL setup
pllclk =
288 MHz
CCLKSEL[7:0]
USBSEL[3:0]
DIVIDER
DIVIDER
CLOCK
CLOCK
UM10237
USB
CPU
© NXP B.V. 2009. All rights reserved.
/6
/4
usbclk =
48 MHz
cclk =
72 MHz
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