OM11077 NXP Semiconductors, OM11077 Datasheet - Page 711

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

1. Basic configuration
2. Introduction
3. Features of the GPDMA
UM10237_4
User manual
The GPDMA is configured using the following registers:
The General Purpose DMA Controller (GPDMA) is an AMBA AHB compliant peripheral
allowing selected LPC2400 peripherals to have DMA support.
1. Power: In the PCONP register
2. Clock: see
3. Interrupts are enabled in the VIC using the VICIntEnable register
4. Initialization: see
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UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA)
controller
Rev. 04 — 26 August 2009
Remark: On reset, the GPDMA is disabled (PCGPDMA = 0).
Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA provides 16 peripheral DMA request lines. Some of these are connected
to peripheral functions that support DMA: the SD/MMC, two SSP, and I2S interfaces.
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time the channel with the
highest priority is serviced first.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. This interface transfers data when a DMA
request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
Internal four-word FIFO per channel.
Table
4–53.
Section
Rev. 04 — 26 August 2009
32–5.
(Table
4–63), set bit PCGPDMA.
(Section
© NXP B.V. 2009. All rights reserved.
User manual
7–3.4).
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