OM11077 NXP Semiconductors, OM11077 Datasheet - Page 732

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 674. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and
UM10237_4
User manual
Bit
4:1
5
9:6
10
13:11 FlowCntrl
14
15
16
17
18
31:19 -
Symbol
SrcPeripheral
-
DestPeriphera
l
-
IE
ITC
L
A
H
DMACC1Configuration - address 0xFFE0 4130) bit description
6.2.7 Lock control
Value Description
0000
0001
0010
0011
0100
0101
0110
0111
or
1xxx
-
-
0
1
0
1
Set the lock bit by programming bit 16 in the DMACCxConfiguration Register.
When a burst occurs, the AHB arbiter must not de-grant the master during the burst until
the lock is deasserted. The GPDMA can be locked for a a single burst such as a long
source fetch burst or a long destination drain burst. The GPDMA does not usually assert
the lock continuously for a source fetch burst followed by a destination drain burst.
is ignored if the source of the transfer is from memory.
SSP0 Tx
SSP0 Rx
SSP1 Tx
SSP1 Rx
SD/MMC
I2S channel 0
I2S channel 1
These values are reserved and should not be used.
Reserved, do not modify, masked on read.
Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory. See the
SrcPeripheral symbol description for values.
Reserved, do not modify, masked on read.
Flow control and transfer type. This value indicates the flow controller and transfer
type. The flow controller can be the GPDMA, the source peripheral, or the
destination peripheral.The transfer type can be memory-to-memory,
memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral.
relevant channel.
Terminal count interrupt mask. When cleared this bit masks out the terminal count
interrupt of the relevant channel.
Lock. When set, this bit enables locked transfers.
Active. This value can be used with the Halt and Channel Enable bits to cleanly
disable a DMA channel. Writing to this bit has no effect.
There is no data in the FIFO of the channel.
The channel FIFO has data.
Halt. The contents of the channel FIFO are drained. This value can be used with the
Active and Channel Enable bits to cleanly disable a DMA channel.
Enable DMA requests.
Ignore further source DMA requests.
Reserved, do not modify, masked on read.
Source peripheral. This value selects the DMA source request peripheral.This field
Interrupt error mask. When cleared this bit masks out the error interrupt of the
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
732 of 792
Reset
Value
0
NA
0
NA
0
0
0
0
0
NA