OM11077 NXP Semiconductors, OM11077 Datasheet - Page 306

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.3 Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004)
If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10,
data does not corrupt for PCD = 4, the minimum value.
The LCD_TIMV register controls the Vertical Synchronization pulse Width (VSW), the
Vertical Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the
Lines-Per-Panel (LPP).
The contents of the LCD_TIMV register are described in
Table 262. Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004)
Bits
31:24
•
PCD = 5 (LCDCLK / 7)
Function
VBP
Rev. 04 — 26 August 2009
Description
Vertical back porch.
This is the number of inactive lines at the start of a frame, after
the vertical synchronization period. The 8-bit VBP field specifies
the number of line clocks inserted at the beginning of each
frame. The VBP count starts immediately after the vertical
synchronization signal for the previous frame has been negated
for active mode, or the extra line clocks have been inserted as
specified by the VSW bit field in passive mode. After this has
occurred, the count value in VBP sets the number of line clock
periods inserted before the next frame. VBP generates 0–255
extra line clock cycles. Program to zero on passive displays for
improved contrast.
Chapter 12: LPC24XX LCD controller
Table
12–262.
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0x0