OM11077 NXP Semiconductors, OM11077 Datasheet - Page 319

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.19 Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)
7.20 Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C)
Table 277. Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04)
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color0 maps through CRSR_PAL0.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
The contents of the CRSR_PAL0 register are described in
Table 278. Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color1 maps through CRSR_PAL1.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
The contents of the CRSR_PAL1 register are described in
Bits
31:2
1
0
Bits
31:24
23:16
15:8
7:0
Function
reserved
FrameSync
CrsrSize
Function
reserved
Blue
Green
Red
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Cursor frame synchronization type.
0 = Cursor coordinates are asynchronous.
1 = Cursor coordinates are synchronized to the frame
synchronization pulse.
Cursor size selection.
0 = 32x32 pixel cursor. Allows for 4 defined cursors.
1 = 64x64 pixel cursor.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Blue color component.
Green color component
Red color component
Chapter 12: LPC24XX LCD controller
Table
Table
12–278.
12–279.
UM10237
© NXP B.V. 2009. All rights reserved.
319 of 792
Reset
value
-
0x0
0x0
Reset
value
-
0x0
0x0
0x0