OM11077 NXP Semiconductors, OM11077 Datasheet - Page 66
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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4. Power domains
UM10237_4
User manual
3.4.10 Power control usage notes
Table 63.
[1]
After every reset, the PCONP register contains the value that enables selected interfaces
and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application might have to access
the PCONP in order to start using some of the on-board peripherals.
Power saving oriented systems should have ones in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
The LPC2400 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the Real Time Clock and the
Battery RAM.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation. Details may be found in
Remark: The RTC and the battery RAM operate independently from each other.
Therefore, the battery RAM can be accessed at any time, regardless of whether the RTC
is enabled or disabled via a dedicated bit in the PCONP register.
Bit
22
23
24
25
26
27
28
29
30
31
LPC247x only.
Symbol
PCTIM2
PCTIM3
PCUART2
PCUART3
PCI2C2
PCI2S
PCSDC
PCGPDMA GP DMA function power/clock control bit.
PCENET
PCUSB
Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
Description
Timer 2 power/clock control bit.
Timer 3 power/clock control bit.
UART 2 power/clock control bit.
UART 3 power/clock control bit.
I
I
SD card interface power/clock control bit.
Ethernet block power/clock control bit.
USB interface power/clock control bit.
2
2
S interface 2 power/clock control bit.
S interface power/clock control bit.
Rev. 04 — 26 August 2009
Chapter 4: LPC24XX Clocking and power control
Section
26–6.6.
UM10237
© NXP B.V. 2009. All rights reserved.
66 of 792
Reset
value
0
0
0
0
1
0
0
0
0
0
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