OM11077 NXP Semiconductors, OM11077 Datasheet - Page 621

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

1. Basic configuration
2. Features
3. Applications
UM10237_4
User manual
The Timer0/1/2/3 peripherals are configured using the following registers:
Remark: The four Timer/Counters are identical except for the peripheral base address. A
minimum of two Capture inputs and two Match outputs are pinned out for all four timers,
with a choice of several pins for each. Timer 1 brings out a third Match output, while
Timers 2 and 3 bring out all four Match outputs.
1. Power: In the PCONP register
2. Peripheral clock: In the PCLK_SEL0 register
3. Pins: Select Timer0/1/2/3 pins and pin modes in registers PINSELn and PINMODEn
4. Interrupts: See register T0/1/2/3MCR
•
•
•
•
•
•
•
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
Rev. 04 — 26 August 2009
Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled
(PCTIM2/3 = 0).
the PCLK_SEL1 register
(see
(Table
the VICIntEnable register
A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
Counter or Timer operation
Up to four 32 bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32 bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.
Interval Timer for counting internal events.
Pulse Width Demodulator via Capture inputs.
Section
24–551) for match and capture events. Interrupts are enabled in the VIC using
9–5).
Rev. 04 — 26 August 2009
(Table
(Table
(Table
4–57), select PCLK_TIMER2/3.
7–106).
4–63), set bits PCTIM0/1/2/3.
(Table
(Table
24–550) and T0/1/2/3CCR
4–56), select PCLK_TIMER0/1; in
© NXP B.V. 2009. All rights reserved.
User manual
621 of 792