OM11077 NXP Semiconductors, OM11077 Datasheet - Page 63

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
3.4.8 Interrupt Wakeup Register (INTWAKE - 0xE01F C144)
Table 60.
Encoding of reduced power modes
The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed.
The encoding of these bits allows backward compatibility with devices that previously only
supported Idle and Power-down modes.
three reduced power modes supported by the LPC2400.
Table 61.
Enable bits in the INTWAKE register allow the external interrupts to wake up the
processor if it is in Power-down mode. The related EINTn function must be mapped to the
pin in order for the wakeup process to take place. It is not necessary for the interrupt to be
enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement
allows additional capabilities, such as having an external interrupt input wake up the
processor from Power-down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power-down without waking the
Bit
4
6:3
7
PM2, PM1, PM0 Description
000
001
101
010
110
Others
-
Symbol
BORD
PM2
Power Mode Control register (PCON - address 0xE01F C0C0) bit description
Encoding of reduced power modes
Power-down mode. Causes the oscillator and all on-chip clocks to be stopped.
A wakeup condition from an external interrupt can cause the oscillator to
re-start, the PD bit to be cleared, and the processor to resume execution. See
Section 4–3.4.3
Deep power-down mode. This is the most extreme power saving mode. As in
Reserved, not currently used.
Description
Brown-Out Reset Disable. When BORD is 1, the second stage of low
voltage detection (2.6 V) will not cause a chip reset.
When BORD is 0, the reset is enabled. The first stage of low voltage
detection (2.9 V) Brown-Out interrupt is not affected.
See
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Power mode control bit 2. See
Normal operation
Idle mode. Causes the processor clock to be stopped, while on-chip peripherals
remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution. See
details.
Sleep mode. This mode is similar to Power-down mode (the oscillator and all
on-chip clocks are stopped), but the flash memory is left in Standby mode. This
allows a more rapid wakeup than Power-down mode because the flash
reference voltage regulator start-up time is not needed. See
details.
Power-down mode, Deep power-down mode causes the oscillator and all
on-chip clocks to be stopped, but also turns off the on-chip DC-DC converter
that supplies power to internal circuitry. See
Section 3–4
Rev. 04 — 26 August 2009
for details.
for details of Brown-Out detection.
Chapter 4: LPC24XX Clocking and power control
Table 4–61
Table 4–61
below shows the encoding for the
for details.
Section 4–3.4.4
Section 4–3.4.1
UM10237
© NXP B.V. 2009. All rights reserved.
Section 4–3.4.2
for details.
63 of 792
Reset
value
0
NA
0
for
for