PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 105

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PIC12C672T-10/SM

Manufacturer Part Number
PIC12C672T-10/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets

Specifications of PIC12C672T-10/SM

Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
1997 Microchip Technology Inc.
The map in
Unimplemented registers will read as '0'.
Figure 6-6: Register File Map
Note 1: Registers in BOLD will be present in every device.
2: These registers may not be implemented, or are implemented as other registers in
3: Not all locations may be implemented. Unimplemented locations will read as ’0’.
4: These locations are unimplemented in Bank1. Access to these unimplemented
some devices.
locations will access the corresponding Bank0 register.
Section 6. Memory Organization
Figure 6-6
Registers
EEDATA
ADCON0 /
EEADR
ADRES /
PCLATH
STATUS
INTCON
Purpose
General
PORTA
PORTB
Bank0
TMR0
INDF
PCL
FSR
shows the register file memory map of some 18-pin devices.
(2)
(2)
(3)
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
7Fh
OPTION_REG 81h
Registers
EECON1
EECON2
ADCON1 /
ADRES /
PCLATH
STATUS
INTCON
Purpose
General
TRISA
TRISB
PCON
Bank1
INDF
PCL
FSR
(2)
(2)
(4)
File
Address
80h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
FFh
DS31006A-page 6-11
6

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