PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 189

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

12.7
12.8
12.9
12.10
INTCON GIE
PIR
PIE
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The placement of this bit is device dependent.
Name
1997 Microchip Technology Inc.
2: These bits may also be named GPIE and GPIF.
Shaded cells are not used by the Timer1 module.
Bit 7
—
Sleep Operation
Resetting Timer1 Using a CCP Trigger Output
Resetting of Timer1 Register Pair (TMR1H:TMR1L)
Timer1 Prescaler
PEIE
Bit 6
—
When Timer1 is configured for asynchronous operation, the TMR1 registers will continue to
increment for each timer clock (or prescale multiple of clocks). When the TMR1 register over-
flows, the TMR1IF bit will get set, and if enabled generate an interrupt that will wake the
processor from sleep mode.
The Timer1 oscillator will add a delta current, due to the operation of this circuitry. That is, the
power-down current will no longer only be the leakage current of the device, but also the active
current of the Timer1 oscillator and other Timer1 circuitry.
If a CCP module is configured in compare mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal resets Timer1.
Timer1 must be configured for either timer or synchronized counter mode to take advantage of
the special event trigger feature. If Timer1 is running in asynchronous counter mode, this reset
operation may not work, and should not be used.
In the event that a write to Timer1 coincides with a special event trigger from the CCP module,
the write will take precedence.
In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period
register for Timer1.
TMR1H and TMR1L registers are not reset on a POR or any other reset, only by the CCP special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset. In any other reset,
the register is unaffected.
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
Table 12-2: Registers Associated with Timer1 as a Timer/Counter
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
Note:
Bit 5
T0IE
The special event trigger from the CCP module does not set interrupt flag bit
TMR1IF.
INTE
Bit 4
TMR1IF
TMR1IE
RBIE
Bit 3
(1)
(1)
(2)
Bit 2
T0IF
Section 12. Timer1
Bit 1
INTF
RBIF
Bit 0
(2)
0000 000x
xxxx xxxx
xxxx xxxx
Value on:
POR,
BOR
0
0
DS31012A-page 12-9
0000 000u
uuuu uuuu
uuuu uuuu
--uu uuuu
Value on
all other
resets
0
0
12