PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 264

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PIC12C672T-10/SM

Manufacturer Part Number
PIC12C672T-10/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets

Specifications of PIC12C672T-10/SM

Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
PICmicro MID-RANGE MCU FAMILY
16.3.7
16.3.8
DS31016A-page 16-14
INTCON
PIR
PIE
SSPBUF
SSPCON
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
Name
2: These bits can also be named GPIE and GPIF.
Shaded cells are not used by the SSP in SPI mode.
Sleep Operation
Effects of a Reset
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
Bit 7
GIE
In master mode all module clocks are halted, and the transmission/reception will remain in that
state until the device wakes from sleep. After the device returns to normal mode, the module will
continue to transmit/receive data.
In slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This
allows the device to be placed in sleep mode, and data to be shifted into the SPI transmit/receive
shift register. When all 8-bits have been received, the SSP interrupt flag bit will be set and if
enabled will wake the device from sleep.
A reset disables the SSP module and terminates the current transfer.
Table 16-1: Registers Associated with SPI Operation
SSPOV
PEIE
Bit 6
SSPEN
Bit 5
T0IE
D/A
INTE
Bit 4
CKP
P
SSPIF
SSPIE
SSPM3
RBIE
Bit 3
S
(1)
(1)
(2)
SSPM2
Bit 2
T0IF
R/W
SSPM1
Bit 1
INTF
UA
SSPM0
RBIF
Bit 0
BF
(2)
1997 Microchip Technology Inc.
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--00 0000 --00 0000
Value on:
POR,
BOR
0
0
Value on
all other
resets
0
0

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