PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 211

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

14.5.1
14.5.2
1997 Microchip Technology Inc.
PWM Period
PWM Duty Cycle
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated
using the following formula:
PWM frequency (F
When TMR2 is equal to PR2, the following three events occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into CCPRxH
The PWM duty cycle is specified by writing to the CCPRxL register and to the DCxB1:DCxB0
(CCPxCON<5:4>) bits. Up to 10-bit resolution is available: the CCPRxL contains the eight MSbs
and CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by DCxB9:DCxB0.
The following equation is used to calculate the PWM duty cycle:
The DCxB9:DCxB0 bits can be written to at any time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2 occurs (which is the end of the current
period). In PWM mode, CCPRxH is a read-only register.
The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle.
This double buffering is essential for glitchless PWM operation.
When CCPRxH and 2-bit latch match the value of TMR2 concatenated with the internal 2-bit
Q clock (or two bits of the TMR2 prescaler), the CCPx pin is cleared. This is the end of the duty
cycle.
Maximum PWM resolution (bits) for a given PWM frequency:
Note:
Note:
PWM duty cycle = (DCxB9:DCxB0 bits value) • Tosc • (TMR2 prescale value), in units of time
PWM period = [(PR2) + 1] • 4 • T
The Timer2 postscaler is not used in the determination of the PWM frequency. The
postscaler could be used to have a servo update rate at a different frequency than
the PWM output.
If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not
be cleared. This allows a duty cycle of 100%.
PWM
) is defined as 1 / [PWM period].
OSC
=
• (TMR2 prescale value), specified in units of time
log
log(2)
(
F
F
PWM
OSC
)
Section 14. CCP
bits
DS31014A-page 14-9
14