PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 184

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
12.3
12.4
12.4.1
DS31012A-page 12-4
External Clock Input Timing for Synchronized Counter Mode
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized Counter Mode
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock
to the timer is F
the internal clock is always synchronized.
Counter mode is selected by setting the TMR1CS bit. In this mode the timer increments on every
rising edge of clock input on the T1OSI pin when the oscillator enable bit (T1OSCEN) is set, or
the T1OSO/T1CKI pin when the T1OSCEN bit is cleared.
If the T1SYNC bit is cleared, then the external clock input is synchronized with internal phase
clocks. The synchronization is done after the prescaler stage. The prescaler is an asynchronous
ripple-counter.
In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is
present, since the synchronization circuit is shut off. The prescaler however will continue to
increment.
When an external clock input is used for Timer1 in synchronized counter mode, it must meet cer-
tain requirements. The external clock requirement is due to internal phase clock (Tosc) synchro-
nization. Also, there is a delay in the actual incrementing of TMR1 after synchronization.
When the prescaler is 1:1, the external clock input is the same as the prescaler output. The syn-
chronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler
output on alternating Tosc clocks of the internal phase clocks. Therefore, it is necessary for the
T1CKI pin to be high for at least 2Tosc (and a small RC delay) and low for at least 2Tosc (and a
small RC delay). Refer to
When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous
ripple-counter prescaler so that the prescaler output is symmetrical. In order for the external
clock to meet the sampling requirement, the ripple-counter must be taken into account. There-
fore, it is necessary for the T1CKI pin to have a period of at least 4Tosc (and a small RC delay)
divided by the prescaler value. Another requirement on the T1CKI pin high and low time is that
they do not violate the minimum pulse width requirements). Refer to
and
47
in the
“Electrical Specifications”
OSC
/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since
parameters
45, 46, and
section.
47
in the
“Electrical Specifications”
1997 Microchip Technology Inc.
parameters
40, 42, 45, 46,
section.