PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 64

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
3.3.1
DS31003A-page 3-14
Power Control (PCON) and STATUS Registers
bit 7
bit 6:3
bit 2
bit 1
bit 0
The Power Control (PCON) register contains a status bit to allow differentiation between a
Power-on Reset (POR) to an external MCLR Reset or WDT Reset. It also contains a status bit to
determine if a Brown-out Reset (BOR) occurred. The power control/status register, PCON has
up to four bits.
The BOR (Brown-out Reset) bit, is unknown on a Power-on-reset. It must initially be set by the
user and checked on subsequent resets to see if BOR = '0' indicating that a Brown-out Reset has
occurred. The BOR status bit is a “don’t care” bit and is not necessarily predictable if the
brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word).
The POR (Power-on Reset) bit, is cleared on a Power-on Reset and is unaffected otherwise. The
user sets this bit following a Power-on Reset. On subsequent resets if POR is ‘0’, it will indicate
that a Power-on Reset must have occurred.
The PER (Parity Error Reset) bit, is cleared on a Parity Error Reset and must be set by user soft-
ware. It will also be set on a Power-on Reset.
The MPEEN (Memory Parity Error Enable) bit, reflects the status of the MPEEN bit in configura-
tion word. It is unaffected by any reset or interrupt.
Register 3-1: PCON Register
bit 7
MPEEN: Memory Parity Error Circuitry Status bit
This bit reflects the value of the MPEEN configuration bit.
Unimplemented: Read as '0'
PER: Memory Parity Error Reset Status bit
1 = No parity error reset occurred
0 = A program memory fetch parity error occurred
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset or
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
MPEEN
Note:
Note:
R-u
(must be set in software after a Power-on Reset or Parity Error Reset occurs)
Power-on Reset occurs)
BOR is unknown on Power-on Reset. It must then be set by the user and checked
on subsequent resets to see if BOR is clear, indicating a brown-out has occurred.
The BOR status bit is a don't care and is not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN bit in the Configuration word).
Not all bits may be implemented.
U-0
—
W = Writable bit
U-0
—
U-0
—
u = unchanged bit
- n = Value at POR reset
U-0
—
R/W-0
PER
1997 Microchip Technology Inc.
R/W-0
POR
bit 0
R/W-0
BOR