PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 297

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

17.4.1.1
1997 Microchip Technology Inc.
Addressing
Once the SSP module has been enabled, it waits for a START condition to occur. Following the
START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled
with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to
the value of the SSPADD register. The address is compared on the falling edge of the eighth clock
(SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events
occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be received by the slave. The five Most Sig-
nificant bits (MSbs) of the first address byte specify if this is a 10-bit address. The R/W bit
(SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For
a 10-bit address the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9 for
slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Table 17-2: Data Transfer Received Byte Actions
Note: Shaded cells show the conditions where the user software did not properly clear the overflow
Transfer is Received
Note:
Status Bits as Data
The SSPSR register value is loaded into the SSPBUF register on the falling edge of the
eighth SCL pulse.
The buffer full bit, BF, is set on the falling edge of the eighth SCL pulse.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF, is set (interrupt is generated if enabled) - on the falling edge
of the ninth SCL pulse.
Receive first (high) byte of Address (the SSPIF, BF, and UA (SSPSTAT<1>) bits are set).
Update the SSPADD register with second (low) byte of Address (clears the UA bit and
releases the SCL line).
Read the SSPBUF register (clears the BF bit) and clear flag bit SSPIF.
Receive second (low) byte of Address (the SSPIF, BF, and UA bits are set).
Update the SSPADD register with the first (high) byte of Address. This will clear the UA bit
and release the SCL line.
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
Receive repeated START condition.
Receive first (high) byte of Address (the SSPIF and BF bits are set).
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
BF
0
1
1
0
condition
Following the Repeated Start condition (step 7) in 10-bit mode, the user only needs
to match the first 7-bit address. The user does not update the SSPADD for the sec-
ond half of the address.
SSPOV
0
0
1
1
Preliminary
SSPSR
Yes
Yes
No
No
SSPBUF
Section 17. MSSP
Generate ACK
Pulse
Yes
No
No
No
(SSP Interrupt occurs
DS31017A-page 17-21
Set bit SSPIF
if enabled)
Yes
Yes
Yes
Yes
17