PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 174

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
11.5
11.5.1
11.5.2
DS31011A-page 11-6
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
External Clock Synchronization
TMR0 Increment Delay
Using Timer0 with an External Clock
External Clock/Prescaler
Output after sampling
External Clock Input or
Prescaler output
Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max.
Increment Timer0 (Q4)
When an external clock input is used for Timer0, it must meet certain requirements as detailed
in
can be synchronized with the internal phase clock (T
incrementing of Timer0 after synchronization.
When no prescaler is used, the external clock input is the same as the prescaler output. The syn-
chronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase clocks
essary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least
2Tosc (and a small RC delay of 20 ns). Refer to
ification of the desired device.
When a prescaler is used, the external clock input is divided by an asynchronous ripple-counter
type prescaler so that the prescaler output is symmetrical. For the external clock to meet the
sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary
for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the pres-
caler value. The only requirement on T0CKI high and low time is that they do not violate the min-
imum pulse width requirement of 10 ns. Refer to
specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from
the time the external clock edge occurs to the time the Timer0 module is actually incremented.
Figure 11-5
Figure 11-5: Timer0 Timing with External Clock
11.5.1 “External Clock Synchronization.”
(2)
Timer0
shows the delay from the external clock edge to the timer incrementing.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(3)
(1)
T0
parameters
These requirements ensure the external clock
parameters
OSC
T0 + 1
). Also, there is a delay in the actual
40,
(Figure
41
40,
and
1997 Microchip Technology Inc.
41
11-5). Therefore, it is nec-
42
and
in the electrical spec-
T0 + 2
42
Small pulse
misses sampling
in the electrical