PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 270

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
16.4.1.3
16.4.1.4
DS31016A-page 16-20
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
Transmission
Clock Arbitration
A7
1
Data in
sampled
A6
2
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit
of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The
ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be
loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should
be enabled by setting the CKP bit (SSPCON<4>). The master must monitor the SCL pin prior to
asserting another clock pulse. The slave devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that
the SDA signal is valid during the SCL high time
An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in
software, and the SSPSTAT register is used to determine the status of the byte transfer. The
SSPIF flag bit is set on the falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of
the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete.
When the not ACK is latched by the slave, the slave logic is reset and the slave then monitors for
another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should
be enabled by setting the CKP bit.
Figure 16-9: I
Clock arbitration has the SCL pin to inhibit the master device from sending the next clock pulse.
The SSP module in I
to the SSP interrupt (SSPIF bit is set and the CKP bit is cleared). The data that needs to be trans-
mitted will need to be written to the SSPBUF register, and then the CKP bit will need to be set to
allow the master to generate the required clocks.
A5
Receiving Address
3
A4
4
A3
5
2
C Waveforms for Transmission (7-bit Address)
A2
6
A1
7
2
C slave mode will hold the SCL pin low when the CPU needs to respond
R/W = 1
8
9
ACK
responds to SSPIF
SCL held low
while CPU
D7
1
SSPBUF is written in software
(Figure
D6
cleared in software
2
Set bit after writing to SSPBUF
D5
3
16-9).
D4
4
Transmitting Data
D3
5
1997 Microchip Technology Inc.
D2
6
From SSP interrupt
service routine
D1
7
D0
8
ACK
9
P