PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 295

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

1997 Microchip Technology Inc.
Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin,
which is the data. Pins that are on the port are automatically configured when the I
enabled. The SSP module functions are enabled by setting SSP Enable bit, SSPEN
(SSPCON1<5>).
The SSP module has six registers for I
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I
(SSPCON1<3:0>) allow one of the following I
• I
• I
• I
Before selecting any I
the appropriate TRIS bits. Selecting an I
and SDA pins to be used as the clock and data lines in I
The SSPSTAT register gives the status of the data transfer. This information includes detection
of a START or STOP bit, specifies if the received byte was data or address, if the next byte is the
completion of 10-bit address, and if this will be a read or write data transfer.
The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register
shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a
double buffered receiver. This allows reception of the next byte to begin before reading the last
byte of received data. When the complete byte is received, it is transferred to the SSPBUF reg-
ister and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and the SSPOV bit (SSPCON1<6>) is set and the byte
in the SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high
byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of
the address needs to be loaded (A7:A0).
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Master mode, clock = OSC/4 (SSPADD +1)
2
C mode, the SCL and SDA pins must be programmed to inputs by setting
Preliminary
2
C operation. They are the:
2
C mode, by setting the SSPEN bit, enables the SCL
2
C modes to be selected:
Section 17. MSSP
2
C operation. Four mode selection bits
2
C mode.
DS31017A-page 17-19
2
C mode is
17