PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 314

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
17.4.11
17.4.11.1 BF Status Flag
17.4.11.2 WCOL Status Flag
17.4.11.3 ACKSTAT Status Flag
DS31017A-page 17-38
I
2
C Master Mode Transmission
Transmission of a data byte, a 7-bit address, or the either half of a 10-bit address is accomplished
by simply writing a value to SSPBUF register. This action will set the buffer full flag bit, BF, and
allow the baud rate generator to begin counting and start the next transmission. Each bit of
address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see
data hold time specification
over count (T
ification
data on the SDA pin must remain stable for that duration and some hold time after the next falling
edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag
is cleared and the master releases SDA allowing the slave device being addressed to respond
with an ACK bit during the ninth bit time, if an address match occurs or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the
master receives an acknowledge, the acknowledge status bit, ACKSTAT, is cleared. If not, the bit
is set. After the ninth clock the SSPIF bit is set, and the master clock (baud rate generator) is
suspended until the next data byte is loaded into the SSPBUF leaving SCL low and SDA
unchanged
After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL
until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock
the master will de-assert the SDA pin allowing the slave to respond with an acknowledge. On the
falling edge of the ninth clock the master will sample the SDA pin to see if the address was rec-
ognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit
(SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the
SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write
to the SSPBUF takes place, holding SCL low and allowing SDA to float.
In transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is
cleared when all 8 bits are shifted out.
If the user writes the SSPBUF when a transmit is already in progress (i.e. SSPSR is still shifting
out a data byte), then WCOL is set and the contents of the buffer are unchanged (the write
doesn’t occur).
WCOL must be cleared in software.
In transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an
acknowledge (ACK = 0), and is set when the slave does not acknowledge (ACK = 1). A slave
sends an acknowledge when it has recognized its address (including a general call), or when the
slave has properly received its data.
parameters
(Figure
BRG
). Data should be valid before SCL is released high (see Data setup time spec-
17-26).
107). When the SCL pin is released high, it is held that way for T
Preliminary
parameters
106). SCL is held low for one baud rate generator roll
1997 Microchip Technology Inc.
BRG
, the