PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 379

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

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20.9
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1997 Microchip Technology Inc.
Comparator Interrupts
Comparator Operation During SLEEP
Effects of a RESET
The comparator interrupt flag is set whenever the comparators value changes relative to the last
value loaded into CMxOUT bits. Software will need to maintain information about the status of
the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred.
The CMIF bit, is the comparator interrupt flag. The CMIF bit must be cleared. Since it is also pos-
sible to set this bit, a simulated interrupt may be initiated.
The CMIE bit and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the
GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the interrupt service routine, can clear the interrupt in the following manner:
a)
b)
An interrupt condition will continue to set the CMIF flag bit. Reading CMCON will end the interrupt
condition, and allow the CMIF flag bit to be cleared.
When a comparator is active and the device is placed in SLEEP mode, the comparator remains
active and the interrupt is functional if enabled. This interrupt will wake up the device from SLEEP
mode when enabled. While the comparator is powered-up, each comparator that is operational
will consume additional current as shown in the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the comparators, CM2:CM0 = 111, before entering
sleep. If the device wakes-up from sleep, the contents of the CMCON register are not affected.
A device reset forces the CMCON register to its reset state. This forces the comparator module
to be in the comparator reset mode, CM2:CM0 = 000. This ensures that all potential inputs are
analog inputs. Device current is minimized when analog inputs are present at reset time. The
comparators will be powered-down during the reset interval.
Any read or write of the CMCON register. This will load the CMCON register with the new
value with the CMxOUT bits.
Clear the CMIF flag bit.
Section 20. Comparator
DS31020A-page 20-9
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