PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 96

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
6.1
6.2
DS31006A-page 6-2
Introduction
Program Memory Organization
There are two memory blocks in the Section 6. Memory Organization; program memory and data
memory. Each block has its own bus, so that access to each block can occur during the same
oscillator cycle.
The data memory can further be broken down into General Purpose RAM and the Special Func-
tion Registers (SFRs). The operation of the SFRs that control the “core” are described here. The
SFRs used to control the peripheral modules are described in the section discussing each indi-
vidual peripheral module.
Mid-Range MCU devices have a 13-bit program counter capable of addressing an 8K x 14 pro-
gram memory space. The width of the program memory bus (instruction word) is 14-bits. Since
all instructions are a single word, a device with an 8K x 14 program memory has space for 8K of
instructions. This makes it much easier to determine if a device has sufficient program memory
for a desired application.
This program memory space is divided into four pages of 2K words each (0h - 7FFh, 800h -
FFFh, 1000h - 17FFh, and 1800h - 1FFFh).
as the 8 level deep hardware stack. Depending on the device, only a portion of this memory may
be implemented. Please refer to the device data sheet for the available memory.
To jump between the program memory pages, the high bits of the Program Counter (PC) must
be modified. This is done by writing the desired value into a SFR called PCLATH (Program
Counter Latch High). If sequential instructions are executed, the program counter will cross the
page boundaries without any user intervention. For devices that have less than 8K words,
accessing a location above the physically implemented address will cause a wraparound. That
is, in a 4K-word device accessing 17FFh actually addresses 7FFh. 2K-word devices (or less) do
not require paging.
Figure 6-1
shows the program memory map as well
1997 Microchip Technology Inc.