PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 71

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Section 4. Architecture
Instruction Pipeline:
The instruction pipeline is a two-stage pipeline which overlaps the fetch and execution of instruc-
tions. The fetch of the instruction takes one T
, while the execution takes another T
. However,
CY
CY
due to the overlap of the fetch of current instruction and execution of previous instruction, an
instruction is fetched and another instruction is executed every single T
.
CY
Single Cycle Instructions:
With the Program Memory bus being 14-bits wide, the entire instruction is fetched in a single
machine cycle (T
). The instruction contains all the information required and is executed in a
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single cycle. There may be a one cycle delay in execution if the result of the instruction modified
the contents of the Program Counter. This requires the pipeline to be flushed and a new instruc-
tion to be fetched.
Reduced Instruction Set:
When an instruction set is well designed and highly orthogonal (symmetric), fewer instructions
are required to perform all needed tasks. With fewer instructions, the whole set can be more rap-
idly learned.
Register File Architecture:
The register files/data memory can be directly or indirectly addressed. All special function regis-
ters, including the program counter, are mapped in the data memory.
Orthogonal (Symmetric) Instructions:
Orthogonal instructions make it possible to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of “special instructions” make programming
simple yet efficient. In addition, the learning curve is reduced significantly. The mid-range instruc-
tion set uses only two non-register oriented instructions, which are used for two of the cores fea-
tures. One is the SLEEP instruction which places the device into the lowest power use mode. The
other is the CLRWDT instruction which verifies the chip is operating properly by preventing the
on-chip Watchdog Timer (WDT) from overflowing and resetting the device.
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1997 Microchip Technology Inc.
DS31004A-page 4-3