PIC12C672T-10/SM Microchip Technology, PIC12C672T-10/SM Datasheet - Page 198

• Manufacturer Part Number: PIC12C672T-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
13.3
13.4
13.5
13.6
13.7
DS31013A-page 13-4
INTCON
PIR
PIE
TMR2
T2CON
PR2
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0'.
Note 1: The position of this bit is device dependent.
Name
Shaded cells are not used by the Timer2 module.
Bit 7
Timer2 module’s register
Timer2 Period Register
GIE
—
Timer Clock Source
Timer (TMR2) and Period (PR2) Registers
TMR2 Match Output
Clearing the Timer2 Prescaler and Postscaler
Sleep Operation
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Bit 6
PEIE
The Timer2 module has one source of input clock, the device clock (F
of 1:1, 1:4 or 1:16 is software selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).
The TMR2 register is readable and writable, and is cleared on all device resets. Timer2 incre-
ments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is
a readable and writable register.
TMR2 is cleared when a WDT, POR, MCLR, or a BOR reset occurs, while the PR2 register is set.
Timer2 can be shut off (disabled from incrementing) by clearing the TMR2ON control bit
(T2CON<2>). This minimizes the power consumption of the module.
The match output of TMR2 goes to two sources:
1.
2.
There are four bits which select the postscaler. This allows the postscaler a 1:1 to 1:16 scaling
(inclusive). After the postscaler overflows, the TMR2 interrupt flag bit (TMR2IF) is set to indicate
the Timer2 overflow. This is useful in reducing the software overhead of the Timer2 interrupt ser-
vice routine, since it will only execute once every postscaler # of matches.
The match output of TMR2 is also routed to the Synchronous Serial Port module, which may soft-
ware select this as the clock source for the shift clock.
The prescaler and postscaler counters are cleared when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset, Watchdog Timer Reset, Brown-out Reset,
During sleep, TMR2 will not increment. The prescaler will retain the last prescale count, ready for
operation to resume after the device wakes from sleep.
Table 13-1: Registers Associated with Timer2
or Parity Error Reset)
Timer2 Postscaler
SSP Clock Input
Note:
Bit 5
T0IE
When T2CON is written TMR2 does not clear.
INTE
Bit 4
TMR2IE
TMR2IF
Bit 3
RBIE
(1)
(1)
Bit 2
T0IF
Bit 1
INTF
Bit 0
RBIF
1997 Microchip Technology Inc.
0000 000x
0000 0000
-000 0000
1111 1111
BOR, PER
Value on:
OSC
POR,
/4). A prescale option
0
0
0000 000u
0000 0000
-000 0000
1111 1111
Value on
all other
resets
0
0