IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part NumberPIC24F16KA102-I/SS
DescriptionIC PIC MCU FLASH 16K 28-SSOP
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 24F
PIC24F16KA102-I/SS datasheets
 


Specifications of PIC24F16KA102-I/SS

Program Memory TypeFLASHProgram Memory Size16KB (5.5K x 24)
Package / Case28-SSOPCore ProcessorPIC
Core Size16-BitSpeed32MHz
ConnectivityI²C, IrDA, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o24Eeprom Size512 x 8
Ram Size1.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 9x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC24F
CorePICData Bus Width16 bit
Data Ram Size1.5 KBInterface TypeI2C/IrDA/SPI/UART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os24
Number Of Timers3Operating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature- 40 COn-chip Adc9-ch x 10-bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithMA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
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PIC24F16KA102 FAMILY
REGISTER 10-2:
DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER
U-0
U-0
U-0
bit 15
R/W-0, HS
U-0
U-0
DSFLT
bit 7
HS = Hardware Settable bit
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
bit 7
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
bit 6-5
Unimplemented: Read as ‘0’
bit 4
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTCC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
bit 1
Unimplemented: Read as ‘0’
bit 0
DSPOR: Power-on Reset Event bit
1 = The V
supply POR circuit was active and a POR event was detected
DD
0 = The V
supply POR circuit was not active, or was active but did not detect a POR event
DD
All register bits are cleared when the DSCON<DSEN> bit is set.
Note 1:
All register bits are reset only in the case of a POR event outside Deep Sleep mode, except bit DSPOR,
2:
which does not reset on a POR event that is caused due to a Deep Sleep exit.
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
3:
DS39927B-page 106
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
DSWDT
DSRTCC
DSMCLR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2,3)
Preliminary
(1)
U-0
R/W-0, HS
DSINT0
bit 8
U-0
R/W-0, HS
(2,3)
DSPOR
bit 0
x = Bit is unknown
© 2009 Microchip Technology Inc.